ST STM32L4+ Series Reference Manual page 1160

Hash processor (HASH)
35.7.2 HASH data input register (HASH_DIN)
Address offset: 0x04
Reset value: 0x0000 0000
HASH_DIN is the data input register. It is 32-bit wide. This register is used to enter the
message by blocks. When the HASH_DIN register is programmed, the value presented on
the AHB databus is 'pushed' into the hash core and the register takes the new value
presented on the AHB databus. To get a correct message format, the DATATYPE bits must
have been previously configured in the HASH_CR register.
When a complete block has been written to the HASH_DIN register, an intermediate digest
calculation is launched:
•
by writing new data into the HASH_DIN register (the first word of the next block) if the
DMA is not used (intermediate digest calculation),
•
automatically if the DMA is used.
When the last block has been written to the HASH_DIN register, the final digest calculation
(including padding) is launched by writing the DCAL bit to 1 in the HASH_STR register (final
digest calculation). This operation is automatic if the DMA is used and MDMAT bit is set to 0.
Reading the HASH_DIN register returns the last word written to this location (zero after
reset).
Note: When the HASH is busy, a write access to the HASH_DIN register might stall the AHB bus if
the digest calculation (intermediate or final) is not complete.
.
31 30 29
rw rw rw
15 14 13
rw rw rw
Bits 31:0 DATAIN[31:0]: Data input
1160/2301
28 27 26 25
rw rw rw rw
12 11 10 9
rw rw rw rw
Writing this register pushes the current register content into the IN FIFO, and the
register takes the new value presented on the AHB databus.
Reading this register returns the current register content.
24 23 22
DATAIN[31:16]
rw rw rw
8 7 6
DATAIN[15:0]
rw rw rw
RM0432 Rev 6
21 20 19 18
rw rw rw rw
5 4 3 2
rw rw rw rw
RM0432
17 16
rw rw
1 0
rw rw