Analog Devices ADSP-SC58 Series Hardware Reference Manual page 1481

DMA Master Channels
The USB controller provides eight DMA master channels.
These channels provide a more efficient transfer of larger amounts of data between the FIFOs and the processor
core, and the channels free up the processor core for other tasks. The processor uses the DMA control registers to
configure and control each of these channels.
Each DMA controller can operate in one of two DMA modes: 0 or 1. When operating in mode 0, the DMA con-
troller can only be programmed to load or unload one packet, so processor intervention is required for each packet
transferred over the USB. The DMA controller can use this mode with any endpoint, whether it uses control, bulk,
isochronous, or interrupt transactions.
When operating in DMA mode 1, the DMA controller can only be programmed to load or unload a complete bulk
transfer, which can be many packets. After set up, the DMA controller loads or unloads the packets, interrupting the
processor only when the transfer has completed. DMA mode 1 can only be used with endpoints that use bulk trans-
actions. It is most valuable where large blocks of data are transferred to a bulk endpoint. The USB protocol requires
splitting such packets into a series of packets of MaxPktSize for the endpoint.
The DMA controller can use mode 1 to avoid the overhead of having to interrupt the processor after each individual
packet. It interrupts the processor only after the transfer completes. In some cases, the block of data transferred con-
sists of a predefined number of these packets that the controlling software counts through the transfer process. In
other cases, the last packet in the series can be less than the maximum packet size. The receiver can use this short
packet to signal the end of the transfer. If the total size of the transfer is an exact multiple of the maximum packet
size, the transmitting software must send a null packet for the receiver to detect.
Each channel can be independently programmed for the selected operating mode.
NOTE:
For bulk OUT transfers using DMA mode 1, the DMA request line is asserted only when:
• There is an edge transition of the state of the USB_EP[n]_RXCSR_H.RXPKTRDY, and
• A payload of MaxPktSize has been received
If a data packet is in the FIFO prior to setting the DMA request mode bits, the DMA request line is not asserted
when the DMA is enabled. DMA is enabled using the USB_DMA[n]_CTL.EN bit. (DMA request mode bits are
USB_EP[n]_RXCSR_H.DMAREQMODE or USB_EP[n]_RXCSR_P.DMAREQMODE). The data is not read
from the Rx FIFO in this situation, resulting in a DMA hang. However, since the packet arrived before DMA re-
quest mode and DMA request enable bits (USB_EP[n]_RXCSR_H.DMAREQEN or
USB_EP[n]_RXCSR_P.DMAREQEN) were enabled, an Rx interrupt is generated for the corresponding end-
point. Therefore, the software must set the DMA request mode to request mode 0 to unload the pre-received pack-
et. The Rx interrupt service routine can be similar to the following:
If
USB_EP[n]_RXCNT
Switch to DMA mode 0 and unload the packet (in mode 0, the DMA request enable is always asserted, whenever
there is data in the FIFO)
Set the
USB_EP[n]_RXCNT
ADSP-SC58x/ADSP-2158x SHARC+ Processor Hardware Reference
= MaxPktSize
to MaxPktSize so as to unload only one packet
USB Programming Model
27–69