Multiprocessor Serial Data Transmission; Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart - Renesas H8SX/1500 Series Hardware Manual

Section 12 Serial Communication Interface (SCI)
12.5.1

Multiprocessor Serial Data Transmission

Figure 12.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Read TDRE flag in SSR
Write transmit data to TDR and
Clear TDRE flag to 0
Read TEND flag in SSR
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0

Figure 12.11 Sample Multiprocessor Serial Transmission Flowchart

Rev. 3.00 Mar. 14, 2006 Page 418 of 804
REJ09B0104-0300
Initialization
Start transmission
TDRE = 1
Yes
set MPBT bit in SSR
All data transmitted?
Yes
TEND = 1
Yes
Break output?
Yes
<End>
[1] SCI initialization:
[1]
The TxD pin is automatically
designated as the transmit data
output pin. After the TE bit is set
to 1, a 1 is output for one frame,
and transmission is enabled.
[2]
[2] SCI status check and transmit
data write:
No
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
No
possible, then write data to TDR,
[3]
and then clear the TDRE flag to 0.
However, the TDRE flag is
checked and cleared
automatically when the DMAC is
initiated by a transmit data empty
interrupt (TXI) request and writes
data to TDR.
No
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the
No
port to 1, clear DR to 0, and then
[4]
clear the TE bit in SCR to 0.