Figure 26.26 Jtag Etck Timing; Table 26.11 Jtag Timing - Renesas H8S Series Hardware Manual

Table 26.11 JTAG Timing

Conditions: V = 3.0 V to 3.6 V, V
CC
Item
ETCK clock cycle time
ETCK clock high pulse width
ETCK clock low pulse width
ETCK clock rise time
ETCK clock fall time
ETRST pulse width
Reset hold transition pulse width
ETMS setup time
ETMS hold time
ETDI setup time
ETDI hold time
ETDO data delay time
Note: When t
*
cyc
ETCK
= 0 V, φ = 4 MHz to 20 MHz
SS
Symbol
t
t
t
t
t
t
t
t
t
t
t
t
≤ t
TCKcyc
t
t
TCKH

Figure 26.26 JTAG ETCK Timing

Min. Max.
50* 250*
TCKcyc

20
TCKH

20
TCKL

5
TCKr

5
TCKf

20
TRSTW

3
RSTHW

20
TMSS

20
TMSH

20
TDIS

20
TDIH

20
TDOD
TCKcyc
t
TCKf
t
TCKL
Rev. 3.00 Jul. 14, 2005 Page 969 of 986
Section 26 Electrical Characteristics
Unit Test Conditions
ns Figure 26.26
t Figure 26.27
cyc
ns Figure 26.28
t
TCKr
REJ09B0098-0300