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15.5.1
Multiprocessor Serial Data Transmission
Figure 15.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Read TDRE flag in SSR
Write transmit data to TDR and
Read TEND flag in SSR
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
Figure 15.11 Sample Multiprocessor Serial Transmission Flowchart
Initialization
Start transmission
TDRE = 1
Yes
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Yes
TEND = 1
Yes
Break output?
Yes
End transmission
Section 15 Serial Communication Interface (SCI)
[1] SCI initialization:
[1]
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
[2]
frame of 1s is output, and
transmission is enabled.
No
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to
0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
No
[3]
be sure to read 1 from the
TDRE flag to confirm that
writing is possible, then write
data to TDR, and then clear the
TDRE flag to 0.
[4] Break output at the end of serial
transmission:
No
To output a break in serial
transmission, set port DDR to 1,
clear DR to 0, and then clear
the TE bit in SCR to 0.
No
[4]
Note:
Do not write to SMR, SCR,
BRR, and SDCR from the
start to the end of
transmission except the
process of [5].
[5]
Rev. 1.00 Apr. 28, 2008 Page 437 of 994
REJ09B0452-0100
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