Table 26.7 Timing Of On-Chip Peripheral Modules - Renesas H8S Series Hardware Manual

Section 26 Electrical Characteristics

Table 26.7 Timing of On-Chip Peripheral Modules

Conditions: V = 3.0 V to 3.6 V, V
CC
Item
I/O ports Output data delay time
Input data setup time
Input data hold time
FRT Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse width
TPU Timer output delay time
Timer input setup time
Timer clock input setup time
Timer clock pulse width
TMR Timer output delay time
Timer reset input setup time
Timer clock input setup time
Timer clock pulse width
PWM, PWMX Timer output delay time
SCI Input clock cycle
Input clock pulse width
Input clock rise time
Input clock fall time
Transmit data delay time (synchronous)
Receive data setup time (synchronous)
Receive data hold time (synchronous)
A/D converter Trigger input setup time
RESO output delay time
WDT
RESO output pulse width
Note: Applied only for the peripheral modules that are available during subclock operation.
*
Rev. 3.00 Jul. 14, 2005 Page 960 of 986
REJ09B0098-0300
= 0 V, φ = 32.768 kHz*, φ = 4 MHz to 20 MHz
SS SUB
Symbol
t
PWD
t
PRS
t
PRH
t
FTOD
t
FTIS
t
FTCS
Single edge t
FTCWH
Both edges t
FTCWL
t
TOCD
t
TICS
t
TCKS
Single edge t
TCKWH
Both edges t
TCKWL
t
TMOD
t
TMRS
t
TMCS
Single edge t
TMCWH
Both edges t
TMCWL
t
PWOD
Asynchronous t
Scyc
Synchronous
t
SCKW
t
SCKr
t
SCKf
t
TXD
t
RXS
t
RXH
t
TRGS
t
RESD
t
RESOW
Min. Max. Unit

50 ns

30

30

50 ns

30

30

1.5 t
cyc

2.5

50 ns

30

30

1.5 t
cyc

2.5

50 ns

30

30

1.5 t
cyc

2.5

50 ns

4 t
cyc

6
0.4 0.6 t
Scyc

1.5 t
cyc

1.5

50 ns

50

50

30 ns

100 ns

132 t
cyc
Test
Conditions
Figure 26.9
Figure 26.10
Figure 26.11
Figure 26.12
Figure 26.13
Figure 26.14
Figure 26.16
Figure 26.15
Figure 26.17
Figure 26.18
Figure 26.19
Figure 26.20
Figure 26.21