Figure 26.20 A/D Converter External Trigger Input Timing; Figure 26.21 Wdt Output Timing (Reso); Table 26.8 Kbu Bus Timing - Renesas H8S Series Hardware Manual

Section 26 Electrical Characteristics
φ
ADTRG

Figure 26.20 A/D Converter External Trigger Input Timing

φ
RESO

Table 26.8 KBU Bus Timing

Conditions: V = 3.0 V to 3.6 V, V
CC
Item
KCLK, KD output fall time
KCLK, KD input data hold time
KCLK, KD input data setup time t
KCLK, KD output delay time
KCLK, KD capacitive load
Note: When KCLK and KD are output, an external pull-up register must be connected, as
*
shown in figure 26.22.
Rev. 3.00 Jul. 14, 2005 Page 964 of 986
REJ09B0098-0300
t
RESD

Figure 26.21 WDT Output Timing (RESO)

= 0 V, φ = 4 MHz to 20 MHz
SS
Symbol Min.
t 20 + 0.1 C
KBF
t 150
KBIH
150
KBIS

t
KBOD

C
b
t
TRGS
t
RESD
t
RESOW
Standard Value
Typ. Max. Unit
 
b
 
 

450

400
Test
Conditions Remarks
ns Figure
26.22
pF