Multiprocessor Serial Data Transmission; Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart - Renesas H8 Series Hardware Manual

14.6.1

Multiprocessor Serial Data Transmission

Figure 14.16 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI3 operations are the same
as those in asynchronous mode.
Start transmission
[1] Read TDRE flag in SSR
Set MPBT bit in SSR
Write transmit data to TDR
[2] All data transmitted?
Read TEND flag in SSR
[3]
Clear PDR to 0 and set PCR to 1
Clear TE bit in SCR3 to 0

Figure 14.16 Sample Multiprocessor Serial Transmission Flowchart

TDRE = 1
Yes
No
TEND = 1
Yes
Break output?
Yes
<End>
Section 14 Serial Communication Interface 3 (SCI3)
[1] Read SSR and check that the TDRE
flag is set to 1, set the MPBT bit in
SSR to 0 or 1, then write transmit
data to TDR. When data is written to
TDR, the TDRE flag is automatically
No
cleared to 0.
[2] To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR. When data is
written to TDR, the TDRE flag is
automatically cleared to 0.
[3] To output a break in serial
transmission, set the port PCR to 1,
clear PDR to 0, then clear the TE bit
Yes
in SCR3 to 0.
No
No
Rev. 1.00 Aug. 28, 2006 Page 233 of 400
REJ09B0268-0100