Table 26.9 I 2 C Bus Timing - Renesas H8S Series Hardware Manual

Section 26 Electrical Characteristics
2
Table 26.9 I C Bus Timing
Conditions: V = 3.0 V to 3.6 V, V
CC
Item
SCL input cycle time
SCL input high pulse width
SCL input low pulse width
SCL, SDA input rise time
SCL, SDA input fall time
SCL, SDA output fall time
SCL, SDA input spike pulse
elimination time
SDA input bus free time
Start condition input hold
time
Retransmission start
condition input setup time
Stop condition input setup
time
Data input setup time
Data input hold time
SCL, SDA capacitive load
Note: * 17.5 t can be set according to the clock selected for use by the I
cyc
Rev. 3.00 Jul. 14, 2005 Page 966 of 986
REJ09B0098-0300
= 0 V, φ = 4 MHz to 20 MHz
SS
Symbol Min.
t 12
SCL
t 3
SCLH
t 5
SCLL

t
Sr

t
Sf
t 20 + 0.1
Of
C
b

t
SP
t 5
BUF
t 3
STAH
t 3
STAS
t 3
STOS
t 0.5
SDAS
t 0
SDAH

C
b
Typ. Max. Unit
 
t
cyc
 
 

7.5*

300 ns

250

1 t
cyc
 
 
 
 
 
 
ns

400 pF
Test Conditions
Figure 26.23
2
C module.