SDA0
V
IH
SDA1
V
IL
t
BUF
SCL0
SCL1
P*
S*
t
Sf
Note: * S, P, and Sr indicate the following conditions:
S: Start condition
P: Stop condition
Sr: Retransmission start condition
Table 26.10 LPC Timing
Conditions:
V
CC
Item
Input clock cycle
Input clock pulse width (H)
Input clock pulse width (L)
Transmit signal delay time
Transmit signal floating delay
time
Receive signal setup time
Receive signal hold time
t
SCLH
t
STAH
t
SCLL
t
Sr
t
SCL
t
SDAH
2
Figure 26.23 I
C Bus Interface Input/Output Timing
= 3.0 V to 3.6V, V
SS
Symbol
t
Lcyc
t
LCKH
t
LCKL
t
TXD
t
OFF
t
RXS
t
RXH
t
STAS
Sr*
= 0 V, φ = 4 MHz to 20 MHz
Min.
Typ.
Max.
30
11
11
2
11
28
7
0
Rev. 3.00 Jul. 14, 2005 Page 967 of 986
Section 26 Electrical Characteristics
t
t
SP
STOS
t
SDAS
Unit
Test Conditions
ns
Figure 26.24
REJ09B0098-0300
P*