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Manuals and User Guides for Renesas 7200 Series. We have
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Renesas 7200 Series manual available for free PDF download: User Manual
Renesas 7200 Series User Manual (303 pages)
MITSUBISHI 8-BIT SINGLE-CHIP MICROCOMPUTER
Brand:
Renesas
| Category:
Computer Hardware
| Size: 2.28 MB
Table of Contents
Table of Contents
7
Chapter 1. Overview
19
Chapter 1. Overview
21
Table 1.1.1 Performance Overview (1)
21
Table 1.1.2 Performance Overview (2)
22
Fig. 1.2.1 Pin Configuration (Top View) (1)
23
Fig. 1.2.2 Pin Configuration (Top View) (2)
24
Table 1.3.1 Pin Description (1)
25
Table 1.3.2 Pin Description (2)
26
Performance Overview
19
Pin Configuration
19
Pin Description
19
Functional Block Diagram
19
Chapter 2. Functional Description
28
Central Processing Unit
28
Accumulator (A)
29
Index Register X (X), Index Register y (Y)
29
Stack Pointer (S)
29
Program Counter (PC)
29
Processor Status Register (PS)
29
Fig. 2.1.1 Registers Configuration Diagram
29
Fig. 2.1.2 CPU Mode Register
30
Chapter 2. Functional Description
31
Fig. 2.1.3 Sequence of Push Onto/Pop from a Stack During Interrupts and Subroutine Calls
32
Fig. 2.1.4 Contents of Stack after Execution of BRK Instruction
34
Access Area
35
Fig. 2.2.1 Access Area of M37221M4-XXXSP and M37221M6-XXXSP/FP
35
Fig. 2.2.2 Access Area of M37221M8-XXXSP and M37221MA-XXXSP
36
Zero Page (Addresses 0000 to 00FF )
37
Special Page (Addresses FF00 to FFFF )
37
Table 2.2.1 Zero
37
Table 2.2.2 Special
37
Fig. 2.3.1 Memory Assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP
38
Memory Assignment
38
Fig. 2.3.2 Memory Assignment of M37221M8-XXXSP and M37221MA-XXXSP
39
Fig. 2.3.3 Memory Map of SFR (Special Function Register) (1)
40
Fig. 2.3.4 Memory Map of SFR (Special Function Register) (2)
41
Fig. 2.3.5 Memory Map of 2 Page Register (Only M37221M8-XXXSP and M37221MA-XXXSP)
42
Internal RAM
43
I/O Ports (Addresses 00C0 to 00CD )
43
Fig. 2.3.6 I/O Setting Example of Port
43
Registers (Addresses 00CE and 00CF )
44
PWM Registers (Addresses 00D0 to 00D4 and 00F6 )
44
PWM Output Control Registers (Addresses 00D5 and 00D6 )
44
Multi-Master I
44
BUS Related Registers
44
To 00DB
44
Serial I/O Related Registers (Addresses 00DC and 00DD )
44
CRT Display Related Registers (Addresses 00E0 to 00EC )
44
A-D Control Register (Addresses 00EE and 00EF )
45
Timer Registers (Addresses 00F0 to 00F3 )
45
Fig. 2.3.7 Access to Timer Registers
45
Timer Mode Registers (Address 00F4 )
46
CPU Mode Register (Address 00FB )
46
Interrupt Request Registers (Addresses 00FC and 00FD )
46
Interrupt Control Registers (Addresses 00FE and 00FF )
46
Page Register (Addresses 0217 to 021B ) (Only M37221M8/MA-XXXSP)
46
CRT Display RAM (Addresses 0600 to 06B7 )
46
ROM (Addresses A000 to FFFF )
46
CRT Display ROM (Addresses 10000 to 11FFF )
46
Input/Output Pins
47
Programmable Ports
47
Table 2.4.1 List of Programmable Port Functions
49
Dedicated Pins
50
Fig. 2.4.1 I/O Pin Block Diagram (1)
51
Fig. 2.4.2 I/O Pin Block Diagram (2)
52
Interrupts
53
Table 2.5.1 Interrupt Sources, Vector Addresses and Priority
53
Interrupt Sources
54
Interrupt Control
56
Fig. 2.5.2 Interrupt Control Logic
56
Fig. 2.5.7 Interrupt Input Polatiry Register (Address 00F9 16 )
59
Fig. 2.5.8 CRT Port Control Register (Address 00EC 16 )
59
Fig. 2.5.10 Interrupt Vector Table
60
Fig. 2.5.9 Interrupt Control System
60
Fig. 2.6.1 Timer 1, Timer 2, Timer 3, and Timer 4 Block Diagram
61
Timer Functions
62
Timers
61
Fig. 2.6.2 Timer Overflow Timing
62
Fig. 2.6.3 Timer 12 Mode Register (Address 00F4 16 )
63
Fig. 2.6.4 Timer 34 Mode Register (Address 00F5 16 )
64
Table 2.6.1 Memory Map of Timer-Related Registers
64
Fig. 2.6.5 Example of Timer System
65
Table 2.6.2 Contents of Timers 3 and 4 When Reset or When Executing STP Instruction
66
Serial I/O
67
Structure of Serial I/O
67
Serial I/O Register (Address 00DD )
67
Fig. 2.7.1 Serial I/O Block Diagram
68
Fig. 2.7.2 Serial I/O Mode Register (Address 00DC 16 )
68
Clock Source Generating Circuit
69
Serial Input/Output Common Transmission/Reception Mode
69
Fig. 2.7.3 Serial Input/Output Common Transfer Mode Block Diagram
69
Table 2.7.1 Clock Source Selection
69
Fig. 2.7.4 Serial I/O Register When Receiving (When SM5 = "0")
70
Serial I/O Data Receive Method (When an Internal Clock Is Selected)
70
Fig. 2.7.5 Serial I/O Register When Transmitting (When SM5 = "0")
71
Serial I/O Data Transmit Method (When an External Clock Is Selected)
71
Note When Selecting a Synchronous Clock
72
Fig. 2.7.6 Timing Diagram of Serial I/O
72
Fig. 2.7.7 Connection Example for Serial I/O Transmit/Receive
73
Fig. 2.7.8 Serial Data Transmit/Receive Processing Sequence
73
Multi-Master I C-BUS Interface
74
Table 2.8.1 Multi-Master I
74
Construction of Multi-Master I
75
BUS Interface
75
Fig. 2.8.1 Block Diagram of Multi-Masteer I
75
Multi-Master I C-BUS Interface-Related Registers
76
Fig. 2.8.2 I C Data Shift Register
76
Fig. 2.8.3 I C Address Register
77
Fig. 2.8.4 I C Clock Control Register
79
Fig. 2.8.5 Connection Port Control by BSEL0 and BSEL1
80
Fig. 2.8.6 I C Control Register
81
Fig. 2.8.7 Interrupt Request Signal Generating Timing
84
Fig. 2.8.8 I C Status Register
84
START Condition, STOP Condition Generation Method
85
Fig. 2.8.10 STOP Condition Generation Timing Diagram
85
Fig. 2.8.9 START Condition Generation Timing Diagram
85
Table 2.8.2 START Condition/Stop Condition Generation Timing Table
85
Fig. 2.8.11 START Condition/Stop Condition Detect Timing Diagram
86
Table 2.8.3 START Condition/Stop Condition Detect Conditions
86
Fig. 2.8.12 Address Data Communication Format
87
A-D Comparator
88
Fig. 2.9.1 A-D Comparator Block Diagram
88
Table 2.9.1 Relationship between Contents of A-D Control Register 2 and Reference
89
Pwm
90
Fig. 2.10.1 14-Bit PWM (DA) Block Diagram
90
Table 2.10.1 PWM Function Performance (at Oscillation Frequency = 8 Mhz)
90
8-Bit PWM Registers (Addresses 00D0 to 00D4 and 00F6 /DA Registers (Addresses 00CE and 00CF )
91
Fig. 2.10.2 8-Bit PWM Block Diagram
91
14-Bit PWM (da Output)
92
Table 2.10.2 the Relation between D
92
Fig. 2.10.3 14-Bit PWM Output Example
93
8-Bit PWM (PWM0 to PWM5: Address 00D0 to 00D4 and 00F6 )
94
14-Bit PWM Output Control
96
8-Bit PWM Output Control
97
CRT Display Function
98
Fig. 2.11.1 Structure of CRT Display Character
98
Table 2.11.1 Outline of CRT Display Function
98
Fig. 2.11.2 CRT Display Circuit Block Diagram
99
Fig. 2.11.3 CRT Control Register (Address 00EA 16 )
100
Display Position
101
Fig. 2.11.4 Count Method of Synchronous Signal
101
Fig. 2.11.5 Display Position
102
Fig. 2.11.6 Vertical Position Register N
103
Fig. 2.11.7 Horizontal Position Register (Address 00E0 16 )
103
Character Size
104
Fig. 2.11.8 Character Size Register (Address 00E4 16 )
104
Fig. 2.11.9 Display Start Position (Horizontal Direction) for each Character Size
104
Table 2.11.2 Relationship between Set Value in Character Size Register and Character Size
104
Memory for Display
105
Fig. 2.11.10 Example of Display Character Data Storing Form
105
Table 2.11.3 Character Code Table (be Omitted Partly)
106
Table 2.11.4 Contents of CRT Display RAM
107
Fig. 2.11.11 Structure of CRT Display RAM
108
Fig. 2.11.12 Color Register N
109
Color Registers
110
Table 2.11.5 Display Example of Character Background Coloring (When Green Is Set for a Character and Blue Is Set for Background Color)
110
Multiline Display
111
Fig. 2.11.13 Generation Timing of CRT Interrupt Request
111
Fig. 2.11.14 Display State of Blocks and Occurrence of CRT Interrupt Request
111
Character Border Function
112
Fig. 2.11.15 Border Example
112
Fig. 2.11.16 Border Selection Register (Address 00E5 16 )
112
Table 2.11.6 Relationship between Set Value of Border Selection Register and Character Border Function
112
CRT Output Pin Control
113
Fig. 2.11.17 CRT Port Control Register (Address 00EC 16 )
113
Raster Coloring Function
114
Fig. 2.11.18 MUTE Signal Output Example
114
Clock for Display
115
Fig. 2.11.19 CRT Clock Selection Register
115
ROM Correction Function
116
Fig. 2.12.1 ROM Correction Address Registers
116
Fig. 2.12.2 ROM Correction Enable Register
116
Software Runaway Detect Function
117
Fig. 2.13.1 Sequence at Detecting Software Runaway Detection
117
Low-Power Dissipation Mode
118
Stop Mode
118
Table 2.14.1 State in Stop Mode
118
Fig. 2.14.1 Oscillation Stabilizing Time at Return by Reset Input
119
Fig. 2.14.2 Execution Sequence Example at Return by Occurrence of INT0 Interrupt Request
119
Wait Mode
120
Interrupts in Low-Power Dissipation Mode
120
Fig. 2.14.3 Reset Input Time
120
Table 2.14.2 State in Wait Mode
120
Table 2.14.3 Invalid Interrupts in the Wait Mode
120
Reset
121
Fig. 2.14.4 State Transitions of Low-Power Dissipation Mode
121
Reset Operation
122
Fig. 2.15.1 Timing Diagram at Reset
122
Internal State Immediately after Reset
123
Fig. 6.7.28 Interrupt Request Register 1
124
Fig. 6.7.29 Interrupt Request Register 2
124
Fig. 6.7.30 Interrupt Control Register 1
124
Fig. 6.7.31 Interrupt Control Register 2
124
Notes for Poweron Reset
126
Fig. 2.15.5 Voltage at Poweron Reset
126
Fig. 2.15.6 Example of Reset Circuit (1)
126
Fig. 2.15.7 Example of Reset Circuit (2)
126
Clock Generating Circuit
127
Fig. 2.16.1 Clock Generating Circuit Block Diagram
127
Oscillation Circuit
128
Fig. 2.17.1 Clock Oscillation Circuit Using a Ceramic Resonator
128
Fig. 2.17.2 External Clock Input Circuit Example
128
Fig. 2.17.3 Clock Oscillation Circuit for CRT Display
128
Chapter 3. Electrical Characteristics
129
Standard Characteristics
129
Fig. 3.1.1 Definition Diagram of Timing on Multi-Master I
133
Chapter 4. M37220M3-Xxxsp/Fp
139
Performance Overview
139
Pin Configuration
139
Pin Description
139
Functional Block Diagram
139
Functional Description
139
Table 4.1.1 Performance Overview (1)
140
Fig. 4.2.1 Pin Configuration (Top View) (1)
142
Fig. 4.2.2 Pin Configuration (Top View) (2)
143
Table 4.3.1 Pin Description (1)
144
Table 4.3.2 Pin Description (2)
145
Table 4.5.1 Difference between M37220M3-XXXSP/FP and M37221M6-XXXSP/FP
147
Access Area
148
Fig. 4.5.1 Access Area
148
Memory Assignment
149
Fig. 4.5.2 Memory Assignment
149
Fig. 4.5.3 Memory Map of SFR (Special Function Register) (1)
150
Fig. 4.5.4 Memory Map of SFR (Special Function Register) (2)
151
Input/Output Pins
152
Table 4.5.2 Difference of Programmable Ports between M37221M6-XXXSP/FP and
152
Interrupts
153
Table 4.5.3 Interrupt Sources, Vector Addresses and Priority
153
Fig. 4.5.5 Interrupt Request Register
154
Fig. 4.5.6 Interrupt Control Register
154
D-A Converter
155
Fig. 4.5.7 D-A Converter Block Diagram
155
Table 4.5.4 Relationship between Contents of D-A Conversion Register and Output Voltage "V
155
Fig. 4.5.8 da N Conversion Register
156
Fig. 4.5.9 Port P3 Output Mode Control Register
156
CRT Display Function
157
Table 4.5.5 Outline of CRT Display Function
157
Fig. 4.5.10 CRT Display Circuit Block Diagram
158
Fig. 4.5.11 Example of Display Character Data Storing Form
159
Table 4.5.6 Character Code Table (be Omitted Partly)
160
Table 4.5.7 Contents of CRT Display RAM
160
Fig. 4.5.12 Structure of CRT Display RAM
161
Fig. 4.5.13 Border Selection Register
162
Fig. 4.5.14 Color Register N
162
Fig. 4.5.15 CRT Control Register
163
Fig. 4.5.16 CRT Port Control Register
163
Internal State Immediately after Reset
164
Electrical Characteristics
166
Standard Characteristics
170
Chapter 5. Application
174
Example of Multi-Line Display
174
Specifications
175
Fig. 5.1.1 Connection Example
175
Fig. 5.1.2 Display Example
175
General Flowchart
176
Line Counter
176
Fig. 5.1.3 Flowchart of Initialization Processing Routine
176
Fig. 5.1.4 Flowchart of V
177
Fig. 5.1.5 Flowchart of CRT Interrupt Processing Routine
178
Fig. 5.1.6 Set of Display Character Data
179
Fig. 5.1.7 Example of Setup Timing for Line Counter and Display Character Data
180
Processing Time
181
Set of Multiple Interrupts
182
Fig. 5.1.8 Timing of Interrupt Processing When Not Setting Multiple Interrupts
182
Fig. 5.1.9 Timing When All Interrupt Request Bits Are "1" at the same Sampling Point
183
Fig. 5.1.10 Flowchart of CRT Interrupt Processing Routine (When Setting Multiple Interrupts)
184
Fig. 5.1.11 Flowchart of V
185
Notes on Programming for OSD (M37220M3-XXXSP/FP)
186
Setting of Color Registers
186
Setting of Border Selection Register
187
Number of Display Characters
187
Fig. 5.2.2 Color Register N (M37220M3-XXXSP/FP)
187
Fig. 5.2.3 Border Selection Register (M37220M3-XXXSP/FP)
187
Usage Example of ROM Correction Function (M37221M8/MA-XXXSP)
188
Connection Example
188
Correction Example
188
Fig. 5.3.1 Connection Example
188
Fig. 5.3.2 Correction Example (1)
188
Fig. 5.3.3 Correction Example (2)
189
E 2 PROM Map
190
Fig. 5.3.4 E 2 PROM Map When Using ROM Correction Function (1)
190
Fig. 5.3.5 E 2 PROM Map When Using ROM Correction Function (2)
191
General Flowchart
192
Fig. 5.3.6 General Flowchart When Using ROM Correction Function
192
Notes on Use
193
Example of I
194
Specifications
194
Connection Example
194
Fig. 5.4.1 Connection Example
194
E 2 PROM Functions
195
Fig. 5.4.2 Byte Write Timing
195
Fig. 5.4.3 Random Address Read Timing
195
General Flowchart
196
Fig. 5.4.4 Flowchart of Write Processing Routine
196
Fig. 5.4.5 Flowchart of Read Processing Routine
197
Fig. 5.4.6 Flowchart of Data Output Processing Routine
198
Example of I
199
Specifications
199
Fig. 5.5.1 Connection Example
199
Single-Chip Color TV Signal Processor Function
200
Fig. 5.5.2 Staus Read Timing
200
Fig. 5.5.3 Byte Write Timing
200
General Flowchart
201
Fig. 5.5.4 Flowchart of Write Processing Routine
201
Fig. 5.5.5 Flowchart of Read Processing Routine
202
Fig. 5.5.6 Flowchart of Data Output Processing Routine
203
Fig. 5.5.7 Flowchart of START Condition Processing Routine
204
Fig. 5.5.8 Flowchart of STOP Condition Processing Routine
204
Fig. 5.5.9 Flowchart of Bus H Processing Routine
204
Fig. 5.5.10 Flowchart of Data Input Processing Routine
205
Fig. 5.5.11 Flowchart of Return ACK Processing Routine
206
Fig. 5.5.12 Flowchart of Return NACK Processing Routine
206
Data Setting According to Key Processing
207
Table 5.5.1 Data Setting at Tuning and Searching
207
Table 5.5.2 Data Setting at "Volume UP/DOWN Key" Input
207
Table 5.5.3 Data Setting at "Screen-Size-Related Keys" Input
207
Table 5.5.4 Data Setting at "Picture Data Control Key" and "Picture Memory Switching Key" Input
207
Table 5.5.5 Data Setting When Changing AFT State
208
Table 5.5.6 Data Setting When Changing Audio Mute State
208
Table 5.5.7 Data Setting When Changing Video Mute State
208
Flowchart of Data Setting According to Key Processing
209
Fig. 5.5.13 Flowchart of Poweron Processing
209
Fig. 5.5.14 Flowchart of "CH UP/DOWN Key" Input Processing
210
Fig. 5.5.15 Flowchart of "Picture Memory Switching Key" Input Processing
211
Register Map
212
Fig. 5.5.16 Status Data Register
212
Fig. 5.5.17 Map of Write Data Register
214
Table 5.5.9 Relationship between DFA and DL TIME
215
Table 5.5.10 Setting of Color System
216
Application Circuit Example
218
Application Circuit Example 1
218
Application Circuit Example 2
219
Chapter 6. Appendix
220
Package Outline
221
Table 6.2.1 Termination of Unused Pins
222
Notes on Use
223
Notes on Processor Status Register
223
Fig. 6.3.1 Initialization of Flags in PS
223
Fig. 6.3.2 Stack Contents after PHP Instruction Execution
223
Fig. 6.3.3 Note When Executing PLP Instruction
223
Notes on Decimal Operation
224
Notes on Interrupts
224
Fig. 6.3.4 Note in Decimal Arithmetic Operation
224
Fig. 6.3.5 Execution of BBC or BBS Instruction
224
Notes on Serial I/O
225
Fig. 6.3.6 Sequence for Switching an External Interrupt Detection Edge
225
Fig. 6.3.7 Initialization for Serial I/O
225
Notes on Timer
226
Fig. 6.3.8 Relation between Timer Values and Their Values Read (Timer Setting Value = 2)
226
Fig. 6.3.9 Relation between Timer Values and Their Values Read When Two Timers Are
226
Notes on A-D Comparator
227
Note on RESET Pin
227
Notes on Input and Output Pins
228
Note on JMP Instruction
228
Note on Multi-Master I
229
BUS Interface
229
Termination of Unused Pins
229
Countermeasures against Noise
230
Shortest Wiring Length
230
Fig.6.4.1 Wiring for RESET Input Pin
230
Fig.6.4.2 Wiring for Clock I/O Pin
230
Fig.6.4.3 Wiring for CNV
231
Fig.6.4.4 Wiring for V
231
Connection of a Bypass Capacitor Across
232
Ss CC
232
SS Line and V CC Line
232
Fig.6.4.5 Bypass Capacitor Across V
232
Fig.6.4.6 Analog Signal Line and Resistor and Capacitor
232
Fig.6.4.7 Wiring for Large Current Signal Line
233
Fig.6.4.8 Wiring for Signal Line Where Potential Levels Charge Frequently
233
Fig.6.4.9 VSS Pattern on Underside of an Oscillator
233
Fig. 6.4.10 Setup for I/O Ports
234
Fig. 6.4.11 Watchidog Timer by Software
235
Chapter 6. Appendix
236
Fig. 6.5.1 Memory Assignment of M37221M4-XXXSP and M37221M6-XXXSP/FP
236
Fig. 6.5.2 Memory Assignment of M37221M8-XXXSP and M37221MA-XXXSP
237
Fig. 6.5.3 Memory Assignment of M37220M3-XXXSP/FP
238
After Reset and
240
Fig. 6.6.1 SFR Assignment
241
Fig. 6.6.5 SFR Assignment
241
Fig. 6.7.23 A-D Control Register 2
241
(Only M37221M8-XXXSP and M37221MA-XXXSP)
243
Chapter 6. Appendix
243
Fig. 6.6.2 SFR Assignment
245
Fig. 6.6.4 SFR Assignment
245
Fig. 6.7.5 PWM Output Control Register 1
245
Fig. 6.7.6 PWM Output Control Register 2
245
Fig. 6.7.1 Port Pi Direction Register
249
Fig. 6.7.2 Port P3 Direction Register
249
Fig. 6.7.3 Port P5 Direction Register
250
Fig. 6.7.4 Port P3 Output Mode Control Register
250
Fig. 6.7.7 I C Data Shift Register
252
Fig. 6.7.8 I C Address Register
252
Fig. 6.7.9 I C Status Register
253
Fig. 6.7.10 I C Control Register
254
Fig. 6.7.11 I C Clock Contorol Register
255
Fig. 6.7.12 Serial I/O Mode Register
256
Fig. 6.7.14 Horizontal Position Register
257
Fig. 6.7.15 Vertical Position Register N
258
Fig. 6.7.16 Character Size Register
258
Fig. 6.7.17 Border Selection Register
259
Fig. 6.7.18 Color Register N
260
Fig. 6.7.19 CRT Control Register
261
Fig. 6.7.20 CRT Port Control Register
262
Fig. 6.7.21 CRT Clock Selection Register
263
Fig. 6.7.24 Timer 12 Mode Register
265
Fig. 6.7.25 Timer 34 Mode Register
266
Fig. 6.7.26 Interrupt Input Polarity Register
266
Fig. 6.7.27 CPU Mode Register
267
Fig. 6.7.32 ROM Correction Enable Register
269
Fig. 6.8.1 I/O Pin Block Diagram (1)
270
Fig. 6.8.2 I/O Pin Block Diagram (2)
271
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