Table 10.3 Clock Input To Tcnt And Count Condition (1) - Renesas H8S/2111B Hardware Manual

Table 10.3 Clock Input to TCNT and Count Condition (1)

Channel CKS2
CKS1
TMR_0 0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
TMR_1 0 0
0 0
0 0
0 1
0 1
0 1
0 1
1 0
Common 1 0
1 1
1 1
Note: If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
*
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.
TCR
CKS0 ICKS1
0 —
1 —
1 —
0 —
0 —
1 —
1 —
0 —
0 —
1 0
1 1
0 0
0 1
1 0
1 1
0 —
1 —
0 —
1 —
STCR
Description
ICKS0
— Disables clock input
0 Increments at falling edge of internal clock
φ/8
1 Increments at falling edge of internal clock
φ/2
0 Increments at falling edge of internal clock
φ/64
1 Increments at falling edge of internal clock
φ/32
0 Increments at falling edge of internal clock
φ/1024
1 Increments at falling edge of internal clock
φ/256
— Increments at overflow signal from
TCNT_1*
— Disables clock input
— Increments at falling edge of internal clock
φ/8
— Increments at falling edge of internal clock
φ/2
— Increments at falling edge of internal clock
φ/64
— Increments at falling edge of internal clock
φ/128
— Increments at falling edge of internal clock
φ/1024
— Increments at falling edge of internal clock
φ/2048
— Increments at compare-match A from
TCNT_0*
— Increments at rising edge of external clock
— Increments at falling edge of external clock
— Increments at both rising and falling edges
of external clock
Rev. 1.00, 05/04, page 193 of 544