External Clock Input In Clock Synchronous Mode - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
Read receive data in RDR
Make transition to software standby mode
Cancel software standby mode
Change operating mode?
<Start data reception>
Figure 15.39 Example of Flowchart for Transition to Software Standby Mode during Reception
15.9.10

External Clock Input in Clock Synchronous Mode

In clock synchronous mode, the external clock SCKn must be input as follows:
High-pulse period, low-pulse period = 2 P1φ clock cycles or more, period = 6 P1φ clock cycles or more
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
<Data reception>
RXI interrupt
Yes
SCR.RE = 0
Yes
Initialization
[ 1 ] Data being received is invalid.
No
[ 1 ]
[ 2 ] Setting for the module standby state is
[ 2 ]
included.
No
SCR.RE = 1
15. Serial Communications Interface
15-64