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8V19N49x Hardware Design Guide
st
VCXO used in the 1
PLL
PDF, Phase detector input frequency
with doubler on
Feedback divider
Suggest Charge pump current setting
Rs
Cs
Cp
4.
Input Output Interface
4.1
Input Termination for Reference Clock Input
The 8V19N490 reference clock input CLK/nCLK is a high-impedance differential receiver. The inverting input
nCLK has weak bias to 1.2V. The input can accept signals from a standard 3.3V LVPECL or an LVDS driver
directly without AC coupling. The board-level termination at the CLK/nCLK input is determined by the driver type.
Figure 13
and
Figure 14
examples of input driven by a differential driver with AC coupling. This section discusses only few examples; other
termination topologies can also be used if desired.
Figure 13. Input Termination Example – 8V19N490 Reference Clock Input CLK/nCLK, Driven by a 3.3V LVPECL Driver
R31UH0005EU0100 Rev.1.0
Jun 3, 2021
nd
Table 3. VCO PLL 2
Suggest range setting
provide examples of input interface without AC coupling.
VCC=3.3V
Zo = 50
Zo = 50
LVPECL Driv er
Order Loop Filter Recommendation
122.88MHz
245.76MHz
12
~ 3.2ma (typical)
600ua to 6.4ma
100 Ohm
Suggest range
(100 to 1k Ohm)
100nF
~ 40pF
VCC=3.3V
R1
R3
133
133
CLK
nCLK
R2
R4
82.5
82.5
30.72MHz
61.44MHz
48
~3.2ma (typical)
Suggest range setting
600ua to 6.4ma
400 Ohm
Suggest range
(100 to 1k Ohm)
100nF
~ 40pF
Figure 15
and
Figure 16
VCC=3.3V
Clock Input
provide
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