Timing Of External Reset On Tcnt; Timing Of Overflow Flag (Ovf) Setting - Renesas H8S Series Hardware Manual

12.3.3

Timing of External RESET on TCNT

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in
TCR. The clear pulse width must be at least 1.5 states. Figure 12-7 shows the timing of this operation.
ø
External reset
input pin
Clear signal
TCNT
12.3.4

Timing of Overflow Flag (OVF) Setting

The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure 12-8 shows the timing
of this operation.
Rev.6.00 Oct.28.2004 page 444 of 1016
REJ09B0138-0600H
N–1
Figure 12-7 Timing of External Reset
ø
TCNT H'FF
Overflow signal
OVF
Figure 12-8 Timing of OVF Setting
N H'00
H'00