Timing Of Input Capture Flag (Icf) Setting; Figure 12.10 Buffered Input Capture Timing (Bufea = 1); Figure 12.11 Timing Of Input Capture Flag (Icfa, Icfb, Icfc, Or Icfd) Setting - Renesas H8S/2158 User Manual

Section 12 16-Bit Free-Running Timer (FRT)
φ
FTIA
Input capture
signal

Figure 12.10 Buffered Input Capture Timing (BUFEA = 1)

12.5.6

Timing of Input Capture Flag (ICF) Setting

The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB,
ICRC, or ICRD). Figure 12.11 shows the timing of setting the ICFA to ICFD flag.
φ
Input capture
signal
ICFA to ICFD
FRC
ICRA to ICRD

Figure 12.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting

Rev. 3.00 Jan 25, 2006 page 304 of 872
REJ09B0286-0300
CPU read cycle of ICRA or ICRC
T 1 T 2
N
N