Timing Of Input Capture Flag Setting; Figure 10.10 Buffered Input Capture Timing (Bufea = 1); Figure 10.11 Timing Of Input Capture Flags (Icfa To Icfd) Setting - Renesas H8S/2437 Hardware Manual

φ
FTIA
Input capture
signal

Figure 10.10 Buffered Input Capture Timing (BUFEA = 1)

10.5.6

Timing of Input Capture Flag Setting

The input capture flag, ICFA, ICFB, ICFC, or ICFD, is set to 1 by the input capture signal. The
FRC value is simultaneously transferred to the corresponding input capture register (ICRA, ICRB,
ICRC, or ICRD). Figure 10.11 shows the timing of setting the ICFA to ICFD flags.
φ
Input capture
signal
ICFA to ICFD
FRC
ICRA to ICRD

Figure 10.11 Timing of Input Capture Flags (ICFA to ICFD) Setting

Rev. 1.00, 09/03, page 256 of 704
CPU read cycle of ICRA or ICRC
T 1 T 2
N
N