Timing Of External Reset On Tcnt; Timing Of Overflow Flag (Ovf) Setting - Renesas H8S/2633 Series Hardware Manual

13.3.3

Timing of External RESET on TCNT

TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 13-7
shows the timing of this operation.
ø
External reset
input pin
Clear signal
TCNT
13.3.4

Timing of Overflow Flag (OVF) Setting

The OVF in TCSR is set to 1 when the timer count overflows (changes from H'FF to H'00). Figure
13-8 shows the timing of this operation.
ø
TCNT
Overflow signal
OVF
644
N–1
Figure 13-7 Timing of External Reset
H'FF
Figure 13-8 Timing of OVF Setting
N H'00
H'00