Appendix C. Number Of Execution States - Renesas H8/300 Series Programming Manual

Appendix C. Number of Execution States

The tables in this appendix can be used to calculate the number of states required for
instruction execution. Table C-1 indicates the number of states required for each cycle
(instruction fetch, branch address read, stack operation, byte data access, word data access,
internal operation). Table C-2 indicates the number of cycles of each type occurring in each
instruction. The total number of states required for execution of an instruction can be
calculated from these two tables as follows:
Execution states = I × S
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @'FFC7
From table C-2:
I = L = 2, J = K = M = N= 0
From table C-1:
S = 8, S = 3
I L
Number of states required for execution = 2 × 8 + 2 × 3 =22
2. JSR @@ 30
From table C-2:
I = 2, J = K = 1,
From table C-1:
S = S = S = 8
I J K
Number of states required for execution = 2 × 8 + 1 × 8 + 1 × 8 = 32
+ J × S + K × S
I J K
L = M = N = 0
+ L × S + M × S
L M
124
+ N × S
N