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7.5.7
Number of DTC Execution States
Table 7.6 lists the execution status for a single DTC data transfer, and table 7.7 shows the number
of states required for each execution status.
Table 7.6
DTC Execution Status
Vector Read
Mode
I
Normal
1
Repeat
1
Block transfer
1
N: Block size (initial setting of CRAH and CRAL)
Table 7.7
Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution
Vector read
status
Register information
read/write
Byte data read
Word data read
Byte data write
Word data write
Internal operation S
The number of execution states is calculated from using the formula below. Note that Σ is the sum
of all transfers activated by one activation source (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · S
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from on-chip ROM to an internal I/O register, then the time required for the
DTC operation is 13 states. The time from activation to the end of data write is 10 states.
Register Information
Read/Write
J
6
6
6
On-Chip RAM
On-Chip RAM
(H'(FF)EC00 to
(On-Chip RAM
H'(FF)EFFF)
other than left)
32
16
1
1
S
—
—
I
1
—
S
J
S
1
1
K
S
1
1
K
S
1
1
L
S
1
1
L
1
1
M
+ Σ (J · S
I
Section 7 Data Transfer Controller (DTC)
Data Read
Data Write
K
L
1
1
1
1
N
N
On-
Chip
On-Chip I/O
ROM
Registers
External Devices
16
8
16
8
1
2
2
2
1
—
—
4
—
—
—
—
1
2
2
2
1
4
2
4
1
2
2
2
1
4
2
4
1
1
1
1
+ K · S
+ L · S
) + M · S
J
K
L
Rev. 3.00 Jan 25, 2006 page 163 of 872
Internal
Operations
M
3
3
3
8
16
16
3
2
3
6 + 2m
2
3 + m
—
—
—
3 + m
2
3 + m
6 + 2m
2
3 + m
3 + m
2
3 + m
6 + 2m
2
3 + m
1
1
1
M
REJ09B0286-0300
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