Number Of Execution States - Renesas H8 Series Hardware Manual

A.3

Number of Execution States

The tables here can be used to calculate the number of states required for instruction execution.
Table A.4 indicates the number of states required for each cycle (instruction fetch, read/write,
etc.), and table A.3 indicates the number of cycles of each type occurring in each instruction. The
total number of states required for execution of an instruction can be calculated from these two
tables as follows:
Execution states = I • S
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S = 2, S = 2
I L
Number of states required for execution = 2 • 2 + 2 • 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
From table A.3:
S = S = S = 2
I J K
Number of states required for execution = 2 • 2 + 1 • 2+ 1 • 2 = 8
Table A.3 Number of Cycles in Each Instruction
Execution Status
(instruction cycle)
Instruction fetch
Branch address read
Stack operation
Byte data access
Word data access
Internal operation
Note: * Depends on which on-chip module is accessed. See section 2.9.1, Notes on Data Access
for details.
+ J • S + K • S + L • S
I J K
L = M = N = 0
On-Chip Memory
S 2
I
S
J
S
K
S
L
S
M
S 1
N
Appendix A CPU Instruction Set
+ M • S + N • S
L M N
Access Location
On-Chip Peripheral Module
—
2 or 3 *
—
Rev. 7.00 Mar 10, 2005 page 545 of 652
REJ09B0042-0700