Number Of Execution States - Renesas H8 Series Hardware Manual

A.3

Number of Execution States

The tables here can be used to calculate the number of states required for instruction execution.
Table A.3 indicates the number of states required for each cycle (instruction fetch, branch address
read, stack operation, byte data access, word data access, internal operation).
Table A.4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables as
follows:
Execution states = I × S
Examples: When instruction is fetched from on-chip ROM, and an on-chip RAM is accessed.
BSET #0, @FF00
From table A.4:
I = L = 2, J = K = M = N= 0
From table A.3:
S = 2, S = 2
I L
Number of states required for execution = 2 × 2 + 2 × 2 = 8
When instruction is fetched from on-chip ROM, branch address is read from on-chip ROM, and
on-chip RAM is used for stack area.
JSR @@ 30
From table A.4:
I = 2, J = K = 1,
From table A.3:
S = S = S = 2
I J K
Number of states required for execution = 2 × 2 + 1 × 2+ 1 × 2 = 8
+ J × S + K × S
I J
L = M = N = 0
Appendix A CPU Instruction Set
+ L × S + M × S + N × S
K L M
Rev. 6.00 Sep 12, 2006 page 435 of 526
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REJ09B0326-0600