Number Of Dtc Execution States - Renesas H8S/2319 series Hardware Manual

Renesas 16-bit single-chip microcomputer
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φ
DTC activation
request
DTC
request
Address
Figure 7-12 DTC Operation Timing (Example of Chain Transfer)
7.3.10

Number of DTC Execution States

Table 7-9 lists execution phases for a single DTC data transfer, and table 7-10 shows the number
of states required for each execution phase.
Table 7-9
DTC Execution Phases
Vector Read
Mode
I
Normal
1
Repeat
1
Block transfer
1
Data transfer
Vector read
Transfer
information
read
Register Information
Read/Write
J
6
6
6
Read Write
Transfer
Transfer
information
information
write
Data Read
K
1
1
N
N: Block size (initial setting of CRAH and CRAL)
Rev. 5.00, 12/03, page 207 of 1088
Data transfer
Read Write
Transfer
information
read
write
Internal
Data Write
Operations
L
M
1
3
1
3
N
3

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