Number Of Dtc Execution States - Renesas H8S Series Hardware Manual

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DTC activation
request
DTC
request
Address
8.3.10

Number of DTC Execution States

Table 8-8 lists execution statuses for a single DTC data transfer, and table 8-9 shows the number of states required for
each execution status.
Table 8-8 DTC Execution Statuses
Mode
Normal
Repeat
Block transfer
Table 8-9 Number of States Required for Each Execution Status
Object to be Accessed
Bus width
Access states
Execution
status
Vector read
Figure 8-12 DTC Operation Timing (Example of Chain Transfer)
Register Information
Vector Read Read/Write
I J
1 6
1 6
1 6
Vector read S
I
Register S
J
information
read/write
Byte data read S
K
Word data read S
K
Byte data write S
L
Word data write S
L
Internal operation S
M
Data transfer
Read Write
Transfer Transfer
information information
read write
Data Read
K
1
1
N
On- On-
Chip Chip On-Chip I/O
RAM ROM Registers
32 16 8 16
1 1 2 2
— 1 — —
1 — — —
1 1 2 2
1 1 4 2
1 1 2 2
1 1 4 2
1
Data transfer
Read Write
Transfer
information information
read
Internal
Data Write Operations
L M
1 3
1 3
N 3
N: Block size (initial setting of CRAH and CRAL)
External Devices
8 16
2 3 2
4 6+2m 2
— — —
2 3+m 2
4 6+2m 2
2 3+m 2
4 6+2m 2
Rev.6.00 Oct.28.2004 page 261 of 1016
Transfer
write
3
3+m
—
3+m
3+m
3+m
3+m
REJ09B0138-0600H