Axi Bus Response Error Interrupt Control Register 0 (Axirerrctl0) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
5.10.7

AXI Bus Response Error Interrupt Control Register 0 (AXIRERRCTL0)

This register controls AXI bus response error interrupts.
Bit:
31
—
Initial value:
0
R/W: R
Bit:
15
—
Initial value: 0
R/W: R
Bit Bit Name
31 to 29 —
28 JCURERR
EN*
27 to 25 —
24 ETHRERR
EN
23 to 9 —
8 CEURERR
EN
7 to 0 —
Note: * This bit is only present in the RZ/A1LU. For the RZ/A1L and RZ/A1LC, the write value should always be 0.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
JCUR
— — — —
ERREN*
0 0 0 0 0
R R R/W R R
14 13 12 11 10
— — — — —
0 0 0 0 0
R R R R R
Initial
Value R/W Description
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Response Error Interrupt Enable for JPEG Codec Unit
Enables or disables interrupt requests when access from the JPEG codec unit
generates a response error.
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Response Error Interrupt Enable for Ethernet Controller
Enables or disables interrupt requests when access from the Ethernet controller
generates a response error.
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
0 R/W Response Error Interrupt Enable for Capture Engine Unit
Enables or disables interrupt requests when access from capture engine unit
generates a response error.
0: Interrupt requests are disabled.
1: Interrupt requests are enabled.
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
25 24 23 22 21
ETHR
— — — —
ERREN
0 0 0 0 0
R R/W R R R
9 8 7 6 5
CEUR
—
— — —
ERREN
0 0 0 0 0
R R/W R R R
5. LSI Internal Bus
20 19 18 17 16
— — — — —
0 0 0 0 0
R R R R R
4 3 2 1 0
—
— — — —
0 0 0 0 0
R R R R R
5-20