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Section 5 Interrupt Controller
Table 5.6
Operations and Control Signal Functions in Each Interrupt Control Mode
Interrupt
Control Mode
INTM1 INTM0
0
0
1
Legend:
O:
Interrupt operation control performed
IM: Used as an interrupt mask bit
PR: Sets priority
—:
Not used
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests other than NMI are masked by ICR and the I bit of
the CCR in the CPU. Note however that the KIN, WUE, and DTI interrupt requests can be
accepted when the I bit is cleared to 0 and are held pending when the I bit is set to 1. Figure 5.5
shows a flowchart of the interrupt acceptance operation.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. According to the interrupt control level specified in ICR, the interrupt controller only accepts
an interrupt request with interrupt control level 1 (priority), and holds pending an interrupt
request with interrupt control level 0 (no priority). If several interrupt requests are issued, an
interrupt request with the highest priority is accepted according to the priority order, an
interrupt handling is requested to the CPU, and other interrupt requests are held pending.
3. If the I bit in CCR is set to 1, only NMI and address break interrupts are accepted by the
interrupt controller, and other interrupt requests are held pending. If the I bit is cleared to 0,
any interrupt request is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except for NMI and address break
interrupts.
Rev. 3.00 Jan 25, 2006 page 92 of 872
REJ09B0286-0300
Interrupt Acceptance Control
Setting
0
O
1
O
3-Level Control
I
UI
ICR
IM
—
PR
IM
IM
PR
Default Priority
Determination
(Trace)
O
O
T
—
—
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