Figure 5.4 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 0 - Renesas H8S/2111B Hardware Manual

7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
IRQ0

Figure 5.4 Flowchart of Procedure up to Interrupt Acceptance in Interrupt Control Mode 0

Program excution state
Interrupt generated?
Yes
An interrupt with interrupt
control level 1?
Yes
No
No
Yes
IRQ1
Yes
IBFI3
Yes
Save PC and CCR
Read vector address
Branch to interrupt handling routine
No
Yes
NMI
No
No
No
IRQ0
Yes
IRQ1
Yes
No
I = 0
Yes
I 1
Hold pending
No
IBFI3
Yes
Rev. 1.00, 05/04, page 81 of 544