Figure 5.4 Flowchart Of Procedure Up To Interrupt Acceptance In Interrupt Control Mode 2 - Renesas H8SX/1500 Series Hardware Manual

32-bit cisc microcomputer
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Yes
No
Level 7 interrupt?
Yes
No
Mask level 6
or below?
Yes
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
Program execution state
Interrupt generated?
Yes
NMI
No
Level 6 interrupt?
Yes
Mask level 5
or below?
Yes
Save PC, CCR, and EXR
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Section 5 Interrupt Controller
No
No
Level 1 interrupt?
No
Yes
Mask level 0?
Yes
Pending
Rev. 3.00 Mar. 14, 2006 Page 115 of 804
No
No
REJ09B0104-0300

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