Analog Devices ADM1060 Manual

Analog Devices ADM1060 Manual

Communications system supervisory/sequencing circuit
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FEATURES
Faults detected on 7 independent supplies
1 high voltage supply (2 V to 14.4 V)
4 positive voltage only supplies (2 V to 6 V)
2 positive/negative voltage supplies
(+2 V to +6 V and –2 V to –6 V)
Watchdog detector input—timeout delay programmable
from 200 ms to 12.8 sec
4 general-purpose logic inputs
Programmable logic block—combinatorial and sequencing
logic control of all inputs and outputs
9 programmable output drivers:
Open collector (external resistor required)
Open collector with internal pull-up to V
Fast internal pull-up to V
Open collector with internal pull-up to VPn
Fast internal pull-up to VPn
Internally charge-pumped high drive (for use with
external N-channel FETs—PDOs 1 to 4 only)
EEPROM—256 bytes of user EEPROM
Industry-standard 2-wire bus interface (SMBus)
Guaranteed PDO low with VPn, VH = 1 V
APPLICATIONS
Central office systems
Servers
Infrastructure network boards
High density, multivoltage system cards
GENERAL DESCRIPTION
The ADM1060 is a programmable supervisory/sequencing
device that offers a single chip solution for multiple power
supply fault detection and sequencing in communications
systems.
In central offices, servers, and other infrastructure systems, a
common backplane dc supply is reduced to multiple board sup-
plies using dc-to-dc converters. These multiple supplies are used
to power different sections of the board, such as 3.3 V logic
circuits, 5 V logic circuits, DSP core, and DSP I/O circuits. There
is usually a requirement that certain sections power up before
others; for example, a DSP core may need to power up before
the DSP I/O, or vice versa, to avoid damage, miscommunication,
or latch-up. The ADM1060 facilitates this, providing supply
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
DD
DD
Communications System
Supervisory/Sequencing Circuit
fault detection and sequencing/combinatorial logic for up to
seven independent supplies. The seven supply fault detectors
consist of one high voltage detector (up to +14.4 V), two bipolar
voltage detectors (up to +6 V or down to −6 V), and four posi-
tive low voltage detectors (up to +6 V). All of the detectors can
be programmed to detect undervoltage, overvoltage, or out-of-
window (undervoltage or overvoltage) conditions. The inputs to
these supply fault detectors are via the VH (high voltage) pin,
VBn (positive or negative) pins, and VPn (positive only) pins.
Either the VH supply or one of the VPn supplies is used to
power the ADM1060 (whichever is highest). This ensures that
in the event of a supply failure, the ADM1060 is kept alive for as
long as possible, thus enabling a reliable fault flag to be asserted
and the system to be powered down in an ordered fashion.
Other inputs to the ADM1060 include a watchdog detector
(WDI) and four general-purpose inputs (GPIn). The watchdog
detector can be used to monitor a processor clock. If the clock
does not toggle (transition from low to high or from high to
low) within a programmable timeout period (up to 18 sec.), a
fail flag will assert. The four general-purpose inputs can be con-
figured as logic buffers or to detect positive/negative edges and
to generate a logic pulse or level from those edges. Thus, the
user can input control signals from other parts of the system
(e.g., RESET or POWER_GOOD) to gate the sequencing of the
supplies supervised by the ADM1060.
The ADM1060 features nine programmable driver outputs
(PDOs). All nine outputs can be configured to be logic outputs,
which can provide multiple functions for the end user such as
RESET generation, POWER_GOOD status, enabling of LDOs,
and watchdog timeout assertion. PDOs 1 to 4 have the added
feature of being able to provide an internally charge-pumped
high voltage for use as the gate drive of an external N-channel
FET that could be placed in the path of one of the supplies
being supervised.
.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.326.8703
© 2003 Analog Devices, Inc. All rights reserved.
ADM1060
(continued on Page 3)
www.analog.com

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Summary of Contents for Analog Devices ADM1060

  • Page 1: 5/03-Data Sheet Changed From Rev. 0 To Rev. A. Changes To Features

    ADM1060 (whichever is highest). This ensures that Fast internal pull-up to V in the event of a supply failure, the ADM1060 is kept alive for as Open collector with internal pull-up to VPn long as possible, thus enabling a reliable fault flag to be asserted...
  • Page 2: Table Of Contents

    ADM1060 TABLE OF CONTENTS General Description ................. 3 PROGRAMMABLE DRIVER OUTPUTS ......33 Specifications..................5 Status/Faults ..................35 Absolute Maximum Ratings............7 FAULT REGISTERS..............38 Typical Performance Characteristics ..........8 MASK REGISTERS..............39 Inputs....................11 Programming .................. 40 SFD REGISTER NAMES............14 WRITE OPERATIONS .............
  • Page 3: General Description

    (PLBA). This PDO7 asserts, and so on. is the logic core of the ADM1060. It is comprised of nine All of the functional capability described here is programmable macrocells, one for each PDO. These macrocells are essentially through the industry-standard 2-wire bus (SMBus) provided.
  • Page 4: Changes To Figure 1

    ADM1060 PROGRAMMABLE ADM1060 DELAY BLOCKS PDB1 PROGRAMMABLE LOGIC BLOCK PDO1 PDO1 ARRAY (PLBA) RISE FALL HIGH SUPPLY (14.4V) PDB2 FAULT DETECTOR PDO2 PDO2 POSITIVE MACROCELL 1 RISE FALL SUPPLY FAULT DETECTOR 1 PDB3 PDO3 PDO3 MACROCELL 2 RISE FALL PDB4...
  • Page 5: Specifications

    ADM1060 SPECIFICATIONS (VH = 4.75 V to 14.4 V, VPn = 3.0 V to 6.0 V, = −40°C to +85°C, unless otherwise noted.) Table 1. Parameter Unit Test Conditions/Comments POWER SUPPLY ARBITRATION VDDCAP Any VPn ≥ 3.0 V VH ≥ 4.75 V 4.75...
  • Page 6 At least one VPn must be ≥3.0 V if used as supply. VH must be ≥4.5 V if used as supply. Specification is not production tested, but is supported by characterization data at initial product release. 1% threshold accuracy is only achievable on parts preprogrammed by Analog Devices. Contact ADM1060.program@analog.com for further details.
  • Page 7: Absolute Maximum Ratings

    ADM1060 ABSOLUTE MAXIMUM RATINGS Table 2. Absolute Maximum Ratings Stresses above those listed under Absolute Maximum Ratings Parameter Rating may cause permanent damage to the device. This is a stress rat- Voltage on VH Pin, PDO Pins 17 V ing only; functional operation of the device at these or any...
  • Page 8: Typical Performance Characteristics

    ADM1060 TYPICAL PERFORMANCE CHARACTERISTICS Figure 2. V vs. V and V Figure 5. I vs. V VDDCAP Figure 3. I vs. V (Supply) Figure 6. I vs. V (Not Supply) –6 –4 –2 –100 –200 –300 –400 Figure 4. I vs.
  • Page 9 ADM1060 1.5% 1.0% = 5V = 4.75V VDDCAP 0.5% 0.0% = 2.7V = 3.3V VDDCAP –0.5% –1.0% –1.5% –40 –25 –10 TEMPERATURE (°C) (µA) LOAD Figure 8. Percent Deviation in V vs. Temperature Figure 11. V (Weak Pull-Up to VP1) vs. Load Current THRESH 14.0...
  • Page 10 ADM1060 –40 –25 –10 TEMPERATURE (°C) Figure 14. Oscillator Frequency vs. Temperature 6.00 5.75 5.50 = 4.75V VDDCAP 5.25 5.00 = 2.7V VDDCAP 4.75 4.50 (µA) LOAD Figure 15. VCCP vs. Load Current = 2.7V VDDCAP = 4.75V VDDCAP –40 –25...
  • Page 11: Inputs

    This loss can be reduced to ~0.2 V, resulting in the ability to power the ADM1060 from a supply as low as 3.0 V. Note that the supply on ON-CHIP SUPPLY the VBn pins cannot be used to power the device, even if the input on these pins is positive.
  • Page 12: Changes To Figure 18

    Only one range (−6 V to −2 V) is available when the SFDs are in negative mode. Note that the bipolar SFDs cannot be used to power the ADM1060, even if the voltage on VBn is positive. Rev. B | Page 12 of 52...
  • Page 13: Changes To Figure 19

    ADM1060 GLITCH FILTER INPUT SFD FAULT TYPES PROGRAMMED TIMEOUT PROGRAMMED TIMEOUT Three types of faults can be asserted by the SFD: an OV fault, a UV fault, and an out-of-window fault (where the UV and OV faults are OR’ed together). The type of fault required is programmed using the fault type select bits (Bits 0, 1 in Register _SnSEL).
  • Page 14: Sfd Register Names

    ADM1060 SFD REGISTER NAMES Table 4. List of Registers for the Supply Fault Detectors Default Address Table Name Power-On Value Description Table 5 BS1OVTH 0xFF Overvoltage Threshold for Bipolar Voltage SFD1 (BS1SFD) Table 6 BS1OVHYST 0x00 Digital Hysteresis on OV Threshold for BS1SFD...
  • Page 15: Sfd Register Bit Maps

    ADM1060 SFD Register Bit Maps BIPOLAR SUPPLY FAIL DETECT (BSn SFD) REGISTERS Table 5. Register 0xA0, 0xA8 BSnOVTH Table 7. Register 0xA2, 0xAA BSnUVTH (Power-On Default 0xFF) (Power-On Default 0x00) Name Description Name Description 7–0 OV7–OV0 8-Bit Digital Value for OV 7–0...
  • Page 16: Change To Table 14

    ADM1060 HIGH VOLTAGE SUPPLY FAULT DETECT (HV SFD) REGISTERS Table 10. Register 0xB0 HSOVTH Table 12. Register 0xB2 HSUVTH (Power-On Default 0xFF) (Power-On Default 0x00) Name Description Name Description 7–0 OV7–OV0 8-Bit Digital Value for OV 7–0 UV7–UV0 8-Bit Digital Value for UV...
  • Page 17: Change To Table 19

    ADM1060 POSITIVE VOLTAGE SUPPLY FAULT DETECT (PSn SFD) REGISTERS Table 15. Register 0xB8, 0xC0, 0xC8, 0xD0 PSnOVTH Table 17. Register 0xBA, 0xC2, 0xCA, 0xD2 PSnUVTH (Power-On Default 0xFF) (Power-On Default 0x00) Name Description Name Description 7−0 OV7−OV0 8-Bit Digital Value for OV Thresh- 7−0...
  • Page 18 WATCHDOG FAULT DETECTOR watchdog signals can be selected as inputs to each of the PLBs The ADM1060 has a watchdog fault detector. This can be used (see the PLBA section). They can also be inverted, if required; to monitor a processor clock to ensure normal operation. The...
  • Page 19 Each of the GPIs can have a weak (10 µA) pull-down current ADM1060 and used to control the status of the PDOs. The source. The current sources can be connected to the inputs by inputs can be simply buffered, or a logic transition can be progamming the relevant bit in the PDEN register.
  • Page 20 ADM1060 Table 24. Registers for the Pull-Down Current Sources on Logic Inputs Hex Address Name Default Power On Value Description PDEN 0x00 Setup of the Pull-Down Current Sources on All Logic Inputs. Pulls the selected input to GND. Table 25. PDEN Register 0x91 Bit Map (Power-On Default 0x00)
  • Page 21: Programming

    (PLBA). This block is the logical core of the device. The PLBA (and the PDBs—see the Programmable Delay Block section) provides the sequencing function of the ADM1060. The asser- tion of the nine programmable driver outputs (PDO) is The last two entries in the truth table show that with the controlled by the PLBA.
  • Page 22: Logic

    ADM1060 LOGIC NOT CONNECTED PLB1 PLB2 INVERT 0x00 P1PLBPOLA.0 IGNORE 0x01 P1PLBIMKA.0 PLB3 INVERT 0x00 P1PLBPOLA.1 IGNORE 0x01 P1PLBIMKA.1 PLB4 INVERT 0x00 P1PLBPOLA.2 IGNORE 0x01 P1PLBIMKA.2 PLB5 INVERT 0x00 P1PLBPOLA.3 IGNORE 0x01 P1PLBIMKA.3 PLB6 INVERT 0x00 P1PLBPOLA.4 IGNORE 0x01 P1PLBIMKA.4...
  • Page 23 ADM1060 The IGNORE bit of all the other inputs (GPIs, PDBs, WDI) The control bits for these macrocells are stored locally in latches in the relevant P1xxxIMK registers is set to 1. Thus, regard- that are loaded at power-up. These latches can also be updated less of its status, the input to the function AND gate for via the serial interface.
  • Page 24 ADM1060 Default Power- Address Table Name On Value Description Table 34 P2GPIIMK 0x00 Polarity sense and ignore mask bits for all four GPIs when used as inputs to the B function of PLB2 Table 35 P2WDICFG 0x00 Polarity sense and ignore mask bits for the pulsed and latched outputs of the...
  • Page 25 ADM1060 Default Power- Address Table Name On Value Description Table 30 P4PLBIMKB 0x00 Ignore mask for all eight other PLB outputs when used as inputs to the B function of PLB4 Table 31 P4SFDPOLB 0x00 Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the B...
  • Page 26 ADM1060 Default Power- Address Table Name On Value Description Table 30 P7PLBIMKA 0x00 Ignore mask for all eight other PLB outputs when used as inputs to the A function of PLB7 Table 31 P7SFDPOLA 0x00 Polarity sense for all seven SFD inputs (VH, two VBs, four VPs) to the A...
  • Page 27 ADM1060 Default Power- Address Table Name On Value Description Table 33 P9GPIPOL 0x00 Polarity sense and ignore mask bits for all four GPIs when used as inputs to the A function of PLB9 Table 34 P9GPIIMK 0x00 Polarity sense and ignore mask bits for all four GPIs when used as inputs...
  • Page 28: Plba Register Bit Maps

    ADM1060 PLBA REGISTER BIT MAPS Table 29. PnPLBPOLA/PnPLBPOLB Registers Bit Map (Power-On Default 0x00) Name Description 7–0 POL9−POL1 If high, invert the PLBn input before it is used in function A or B. PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7...
  • Page 29 ADM1060 Table 32. PnSFDIMKA/PnSFDIMKB Registers Bit Map (Power-On Default 0x00) Name Description Reserved Cannot Be Used 6−0 IGN7−IGN1 If high, mask the SFDn input before it is used in function A or B. PLB1 PLB2 PLB3 PLB4 PLB5 PLB6 PLB7...
  • Page 30 ADM1060 Table 34. PnGPIIMK Registers Bit Map (Power-On Default 0x00) Name Description 7−4 AIMK4−AIMK1 If high, mask the GPIn input before it is used in function A. 3−0 BIMK4−BIMK1 If high, mask the GPIn input before it is used in function B.
  • Page 31 ADM1060 PROGRAMMABLE DELAY BLOCK PDB INPUT Each output of the PLBA is fed into a separate programmable PROGRAMMED PROGRAMMED RISE TIME PROGRAMMED RISE TIME delay block (PDB). The PDB enables the user to add a delay to FALL TIME = 0...
  • Page 32 ADM1060 Table 37. Programmable Delay Block (PDB) Registers Default Power-On Addr. Table Name Value Description Table 38 P1PDBTIM 0x00 Delay for PDB1. Delay for rising edge and falling edge programmed separately. Table 38 P2PDBTIM 0x00 Delay for PDB2. Delay for rising edge and falling edge programmed separately.
  • Page 33: Outputs

    • The (delayed) output from the associated PLB (enabled by PROGRAMMABLE DRIVER OUTPUTS setting bit CFG4 to 1) The ADM1060 has nine programmable driver outputs (PDOs). • Data that is driven directly over the SMBus interface (enabled These are the logic outputs of the device. Each PDO is normally by setting Bit CFG5 to 1).
  • Page 34: Change To Table 40

    ADM1060 Table 39. Programmable Driver Outputs Registers Default Power-On Address Table Name Value Description Table 40 P1PDOCFG 0x00 Selects the format of the PDO1 output (open drain, open drain with internal pull-up, charge pumped, etc.). Table 40 P2PDOCFG 0x00 Selects the format of the PDO2 output (open drain, open drain with internal pull-up, charge pumped, etc.).
  • Page 35: Status/Faults

    “fault plane” consisting of two registers, LATF1 and ANYFLT. As long as ANYFLT remains at 0, only the content of LATF2, that the system controller can read out of the ADM1060 LATF1 is read. There are two reasons for this. The first is that via the SMBus.
  • Page 36 ADM1060 The functionality of the fault plane is best illustrated with an 5. VP1 at 4.2 V: LATF1 = 10000000, LATF2 = 00000000. At first example. For instance, take VP1 to have an input supply of 5.0 V. glance, this would appear to be incorrect since the SFD out- A UV/OV window of 4.5 V to 5.5 V is set up on VP1.
  • Page 37 ADM1060 Table 44. Bit Map for OVSTAT Register 0xD9 (Power-On Default 0x00) Name Description Reserved Cannot Be Used VP4OV If high, voltage on VP4 input is higher than the OV threshold. VP3OV If high, voltage on VP3 input is higher than the OV threshold.
  • Page 38: Fault Registers

    ADM1060 FAULT REGISTERS Table 49. List of Fault Registers Hex Addr. Table Name Default Power On Value Description Table 50 LATF1 0x00 Fault Status Register for the seven SFDs Table 51 LATF2 0x00 Fault Status Register for the four GPIs and the Watchdog Detector Table 50.
  • Page 39: Mask Registers

    ADM1060 MASK REGISTERS Table 52. List of Mask Registers Hex Addr. Table Name Default Power On Value Description Table 53 ERRMASK1 0x00 Error Mask Register for the seven SFDs Table 54 ERRMASK2 0x00 Error Mask Register for the four GPIs and the Watchdog Detector Table 53.
  • Page 40: Programming

    SMBus. may wish to alter the configuration of functions on the ADM1060; for example, change the UV or OV limit of an SFD, The bit map for register UPDCFG is shown in Table 56. A flow the fault output of an SFD, the timeout of the watchdog detec- chart for download at power-up and subsequent configuration tor, the rise time delay of one of the PDOs, and so on.
  • Page 41 If set high, the ADM1060 will download the buffered RAM register data into the local latches. This bit self-clears (returns to 0) after the download. If set high, the ADM1060 will update its configuration in real time as a word is written to a local RAM register via the SMBus.
  • Page 42 0xF800 to 0xF9FF. This may be used for permanent defines specific conditions for different types of read and write storage of data that will not be lost when the ADM1060 is pow- operation, which are discussed later. The general SMBus proto- ered down, unlike the data in the volatile registers.
  • Page 43: Changes To Figure 25-26

    EEPROM is arranged as 16 pages of 32 bytes, and an entire SMBus PROTOCOLS FOR RAM AND EEPROM page must be erased. The ADM1060 contains volatile registers (RAM) and nonvola- Page erasure is enabled by setting Bit 3 in register UPDCFG tile EEPROM. User RAM occupies address locations from 0x00 (address 0x90) to 1.
  • Page 44: Write Operations

    6. The master asserts a STOP condition on SDA and the trans- action ends. 7. The slave asserts ACK on SDA. In the ADM1060, the send byte protocol is used for two 8. The master sends a data byte (or may assert STOP at this purposes: point).
  • Page 45: Read Operations

    The start address for a block write must previously slave device, as follows: have been set. In the case of the ADM1060, this is done by a 1. The master device asserts a START condition on SDA. Send Byte operation to set a RAM address or a Write Byte/Word operation to set an EEPROM address.
  • Page 46 The start address for a block read must previously error correction) byte after a write to RAM, a write to have been set. In the case of the ADM1060, this is done by a EEPROM, a block write to RAM/EEPROM, or a block read Send Byte operation to set a RAM address, or a Write from RAM/EEPROM.
  • Page 47: Changes To Figure 37

    PDO2 PDO3 PDO4 ADM1060 PDO5 PWR_OK PDO6 PDO7 GPI1 PDO8 GPI2 GPI3 PDO9 PWRGD GPI4 VOUT CLKOUT 0.9V_OUT 1.8V 3.3V VIN_CORE VOUT DC/DC µP CONVERTER –5V_OUT VOUT INVERTER Figure 37. ADM1060 Application Diagram Rev. B | Page 47 of 52...
  • Page 48 ADM1060 Table 57. ADM1060 Register Map BLOCK PLB1 0 P1PLBPOLA P1PLBIMKA P1SFDPOLA P1SFDIMKA P1GPIPOL P1GPIIMK P1WDICFG P1EN P1PLBPOLB P1PLBIMKB P1SFDPOLB P1SFDIMKB P1PDBTIM P1PDOCFG PLB2 1 P2PLBPOLA P2PLBIMKA P2SFDPOLA P2SFDIMKA P2GPIPOL P2GPIIMK P2WDICFG P2EN P2PLBPOLB P2PLBIMKB P2SFDPOLB P2SFDIMKB P2PDBTIM P2PDOCFG PLB3...
  • Page 49: Changes To Table 58

    High Voltage Supply Input. Two input ranges. A supply of between 2 V and 6 V or between 4.8 V and 14.4 V can be applied to this pin. The V arbitrator will select this supply to power the ADM1060 if it is the highest supply supervised.
  • Page 50: Updated Outline Dimensions

    ADM1060ARU–REEL –40°C to +85°C 28-lead TSSOP RU-28 ADM1060ARU–REEL7 –40°C to +85°C 28-lead TSSOP RU-28 EVAL–ADM1060EB Evaluation Board Contact factory for availability of the evaluation board. For general ADM1060 support, send email to: ADM1060.support@analog.com Rev. B | Page 50 of 52...
  • Page 51 ADM1060 NOTES Rev. B | Page 51 of 52...
  • Page 52 ADM1060 NOTES © 2003 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. C03470–0–12/03(B) Rev. B | Page 52 of 52...

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