Appendix; I/O Port States In Each Pin State; Table A.1 I/O Port States In Each Pin State - Renesas H8S Series Hardware Manual

A.

I/O Port States in Each Pin State

Table A.1 I/O Port States in Each Pin State
MCU
Port Name Operating
Pin Name Mode
Port 1 2, 3
Port 2 2, 3
Port 3 2, 3
Port 4 2, 3
Port 50 2, 3
ExEXCL
Port 51, 52 2, 3
Port 6 2, 3
Port 7, E 2, 3
Port 8 2, 3
Port 97 2, 3
Port 96 2, 3
φ,
EXCL
Port 95 to 90 2, 3
Port A to D, 2, 3
F, G
[Legend]
H: High level
L: Low level
T: High impedance
keep: Input ports are in the high-impedance state (when DDR = 0 and PCR = 1, the input pull-up
MOS remains on).
Output ports maintain their previous state.
Depending on the pins, the on-chip peripheral modules may be initialized and the I/O port
function determined by DDR and DR.
DDR: Data direction register

Appendix

Hardware Software
Standby Standby
Reset Mode Mode
T T keep
T T keep
T T keep
T T keep
T T keep
T T keep
T T keep
T T T
T T keep
T T keep
T T [DDR = 1]H
[DDR = 0]T
T T keep
T T keep
Watch Sleep
Mode Mode
keep keep
keep keep
keep keep
keep keep
ExEXCL keep
input
/keep
keep keep
keep keep
T T
keep keep
keep keep
EXCL [DDR = 1]
input/ Clock output
keep [DDR = 0]T
keep keep
keep keep
Rev. 3.00 Jul. 14, 2005 Page 975 of 986
Appendix
Sub- Sub- Program
Sleep Active Execution
Mode Mode State
keep I/O port I/O port
keep I/O port I/O port
keep I/O port I/O port
keep I/O port I/O port
ExEXCL ExEXCL ExEXCL
input/ input/ input/
keep I/O port I/O port
keep I/O port I/O port
keep I/O port I/O port
T Input port Input port
keep I/O port I/O port
keep I/O port I/O port
EXCL EXCL Clock output/
input/ input/ EXCL input/
keep Input port input port
keep I/O port I/O port
keep I/O port I/O port
REJ09B0098-0300