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Section 7 Refresh Controller
RTCNT is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCNT is initialized
to H'00 by a reset and in standby mode.
7.2.4
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that determines the interval at which RTCNT is
compare matched.
Bit
7
Initial value
1
Read/Write
R/W
RTCOR and RTCNT are constantly compared. When their values match, the CMF flag is set to 1
in RTMCSR, and RTCNT is simultaneously cleared to H'00.
RTCOR is write-disabled when the PSRAME bit or DRAME bit is set to 1. RTCOR is initialized
to H'FF by a reset and in hardware standby mode. In software standby mode it retains its previous
value.
Rev. 3.00 Mar 21, 2006 page 154 of 814
REJ09B0302-0300
6
5
4
1
1
1
R/W
R/W
R/W
3
2
1
1
R/W
R/W
R/W
1
0
1
1
R/W
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