Table of Contents
Advertisement
Section 13 8-Bit Timer (TMR)
13.3.1
Timer Counter (TCNT)
Each TCNT is an 8-bit readable/writable up-counter. TCNT_0 and TCNT_1 (or TCNT_Y and
TCNT_X) comprise a single 16-bit register, so they can be accessed together by word access. The
clock source is selected by the CKS2 to CKS0 bits in TCR. TCNT can be cleared by an external
reset input signal, compare-match A signal or compare-match B signal. The method of clearing
can be selected by the CCLR1 and CCLR0 bits in TCR. When TCNT overflows (changes from
H'FF to H'00), the OVF bit in TCSR is set to 1. TCNT is initialized to H'00.
13.3.2
Time Constant Register A (TCORA)
TCORA is an 8-bit readable/writable register. TCORA_0 and TCORA_1 (or TCORA_Y and
TCORA_X) comprise a single 16-bit register, so they can be accessed together by word access.
TCORA is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag A (CMFA) in TCSR is set to 1. Note however that comparison
is disabled during the T2 state of a TCORA write cycle. The timer output from the TMO pin can
be freely controlled by these compare-match A signals and the settings of output select bits OS1
and OS0 in TCSR. TCORA is initialized to H'FF.
13.3.3
Time Constant Register B (TCORB)
TCORB is an 8-bit readable/writable register. TCORB_0 and TCORB_1 (or TCORB_Y and
TCORB_X) comprise a single 16-bit register, so they can be accessed together by word access.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding compare-match flag B (CMFB) in TCSR is set to 1. Note however that comparison
is disabled during the T2 state of a TCORB write cycle. The timer output from the TMO pin can
be freely controlled by these compare-match B signals and the settings of output select bits OS3
and OS2 in TCSR. TCORB is initialized to H'FF.
Rev. 3.00 Jan 25, 2006 page 320 of 872
REJ09B0286-0300
Advertisement
Table of Contents
