Refresh Timer Counter (Rtcnt); Refresh Time Constant Register (Rtcor) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
8.4.6

Refresh Timer Counter (RTCNT)

RTCNT is an 8-bit counter that increments using the clock selected by bits CKS[2:0] in RTCSR. When RTCNT matches
RTCOR, RTCNT is cleared to 0. The value in RTCNT returns to 0 after counting up to 255. When the RTCNT is written,
the upper 16 bits of the write data must be H'A55A to cancel write protection.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 8 ―
7 to 0
8.4.7

Refresh Time Constant Register (RTCOR)

RTCOR is an 8-bit register. When RTCOR matches RTCNT, the CMF bit in RTCSR is set to 1 and RTCNT is cleared to
0.
When the RFSH bit in SDCR is 1, a memory refresh request is issued by this matching signal. This request is maintained
until the refresh operation is performed. If the request is not processed when the next matching occurs, the previous
request is ignored.
When the CMIE bit in RTCSR is set to 1, an interrupt request is issued by this matching signal. The request continues to
be output until the CMF bit in RTCSR is cleared. Clearing the CMF bit only affects the interrupt request and does not
clear the refresh request. Therefore, a combination of refresh request and interval timer interrupt can be specified so that
the number of refresh requests are counted by using timer interrupts while refresh is performed periodically.
When RTCOR is written, the upper 16 bits of the write data must be H'A55A to cancel write protection.
Bit: 31
-
Initial value: 0
R/W: R
Bit: 15
-
Initial value: 0
R/W: R
Bit Bit Name
31 to 8 ―
7 to 0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
All 0 R/W
30 29 28 27 26
- - - - -
0 0 0 0 0
R R R R R
14 13 12 11 10
- - - - -
0 0 0 0 0
R R R R R
Initial
Value R/W
All 0 R
All 0 R/W
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- -
0 0 0 0 0
R R R/W R/W R/W
Description
Reserved
These bits are always read as 0.
8-Bit Counter
25 24 23 22 21
- - - - -
0 0 0 0 0
R R R R R
9 8 7 6 5
- -
0 0 0 0 0
R R R/W R/W R/W
Description
Reserved
These bits are always read as 0.
8-Bit Counter
8. Bus State Controller
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
20 19 18 17 16
- - - - -
0 0 0 0 0
R R R R R
4 3 2 1 0
0 0 0 0 0
R/W R/W R/W R/W R/W
8-30