Table 10.3 Cclr2 To Cclr0 (Channels 0 And 3); Table 10.4 Cclr2 To Cclr0 (Channels 1, 2, 4, And 5) - Renesas H8S/2368 Series Hardware Manual

Table 10.3 CCLR2 to CCLR0 (Channels 0 and 3)

Bit 7
Channel CCLR2
0, 3 0
1
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
*2 When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.

Table 10.4 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)

Bit 7
Channel Reserved*
1, 2, 4, 5 0
Notes: *1 Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
*2 Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Bit 6 Bit 5
CCLR1 CCLR0
0 0
1
1 0
1
0 0
1
1 0
1
Bit 6 Bit 5
2
CCLR1 CCLR0
0 0
1
1 0
1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
2
capture*
TCNT cleared by TGRD compare match/input
2
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Rev. 2.00, 05/03, page 381 of 820
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