Table 18.3 Cclr0 To Cclr2 (Channels 0, 3, And 4); Table 18.4 Cclr0 To Cclr2 (Channels 1 And 2) - Renesas HD6417641 Hardware Manual

Table 18.3 CCLR0 to CCLR2 (Channels 0, 3, and 4)

Bit 7
Channel CCLR2
0, 3, 4 0
1
Notes: 1. Synchronous operation is set by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.

Table 18.4 CCLR0 to CCLR2 (Channels 1 and 2)

Bit 7
Channel Reserved*
1, 2 0
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1 and 2. This bit is always read as 0 and cannot be
modified.
Bit 6 Bit 5
CCLR1 CCLR0
0 0
1
1 0
1
0 0
1
1 0
1
Bit 6 Bit 5
2
CCLR1 CCLR0
0 0
1
1 0
1
Section 18 Multi-Function Timer Pulse Unit (MTU)
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
2
capture*
TCNT cleared by TGRD compare match/input
2
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Rev. 4.00 Sep. 14, 2005 Page 525 of 982
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