Table 9.5 Cclr2 To Cclr0 (Channels 0 And 3); Table 9.6 Cclr2 To Cclr0 (Channels 1, 2, 4, And 5) - Renesas H8SX/1500 Series Hardware Manual

Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.5 CCLR2 to CCLR0 (Channels 0 and 3)
Bit 7
Channel CCLR2
0, 3 0
0
0
0
1
1
1
1
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 9.6 CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
2
Bit 7*
Channel Reserved
1, 2, 4, 5 0
0
0
0
Notes: 1. Synchronous operation is selected by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is a read-only bit and cannot be modified.
Rev. 3.00 Mar. 14, 2006 Page 266 of 804
REJ09B0104-0300
Bit 6 Bit 5
CCLR1 CCLR0
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
Bit 6 Bit 5
CCLR1 CCLR0
0 0
0 1
1 0
1 1
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
TCNT clearing disabled
TCNT cleared by TGRC compare match/input
2
capture*
TCNT cleared by TGRD compare match/input
2
capture*
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
Description
TCNT clearing disabled
TCNT cleared by TGRA compare match/input
capture
TCNT cleared by TGRB compare match/input
capture
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
synchronous operation*
1
1
1