Timer Output Control Register 1 (Tocr1) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
10.3.17

Timer Output Control Register 1 (TOCR1)

TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle output in complementary
PWM mode/reset synchronized PWM mode, and controls output level inversion of PWM output.
Bit Bit Name
7 —
6 PSYE
5, 4 —
3 TOCL
2 TOCS
1 OLSN
0 OLSP
Note 1. Setting the TOCL bit to 1 prevents accidental modification when the CPU goes out of control.
Note 2. Clearing the TOCS bit to 0 makes this bit setting valid.
Note 3. After power-on reset, 1 can be written only once. After 1 has been written, 0 cannot be written.
Note 4. If the dead-time is not generated, the negative-phase output will be the exact inverse of the positive-phase output. Furthermore,
set OLSP and OLSN to the same value.
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit:
7 6
- PSYE
Initial value:
0 0
R/W:
R R/W
Initial
value R/W Description
0 R Reserved
This bit is always read as 0. The write value should always be 0.
0 R/W PWM Synchronous Output Enable
This bit selects the enable/disable of toggle output synchronized with the PWM
period.
0: Toggle output is disabled
1: Toggle output is enabled
All 0 R Reserved
These bits are always read as 0. The write value should always be 0.
3
0 R/(W)* TOC Register Write Protection*
This bit selects the enable/disable of write access to the TOCS, OLSN, and
OLSP bits in TOCR1.
0: Write access to the TOCS, OLSN, and OLSP bits is enabled
1: Write access to the TOCS, OLSN, and OLSP bits is disabled
0 R/W TOC Select
This bit selects either the TOCR1 or TOCR2 setting to be used for the output
level in complementary PWM mode and reset-synchronized PWM mode.
0: TOCR1 setting is selected
1: TOCR2 setting is selected
0 R/W Output Level Select N*
This bit selects the negative phase output level in reset-synchronized PWM
mode/complementary PWM mode. See Table 10.28.
0 R/W Output Level Select P*
This bit selects the positive phase output level in reset-synchronized PWM
mode/complementary PWM mode. See Table 10.29.
5 4 3 2 1
- - TOCL TOCS OLSN
0 0 0 0 0
3
R R R/(W)* R/W R/W
1
2 4
*
2
10. Multi-Function Timer Pulse Unit 2
0
OLSP
0
R/W
10-46