Timer Output Control Register (Tocr) - Renesas F-ZTAT H8 Series Hardware Manual

10.2.6

Timer Output Control Register (TOCR)

TOCR is an 8-bit readable/writable register that selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized PWM mode, and inverts the output levels.
Bit 7
—
Initial value 1
Read/Write —
The settings of the XTGD, OLS4, and OLS3 bits are valid only in complementary PWM mode
and reset-synchronized PWM mode. These settings do not affect other modes.
TOCR is initialized to H'FF by a reset and in standby mode.
Bits 7 to 5—Reserved: Read-only bits, always read as 1.
Bit 4—External Trigger Disable (XTGD): Selects externally triggered disabling of ITU output
in complementary PWM mode and reset-synchronized PWM mode.
Bit 4: XTGD Description
0 Input capture A in channel 1 is used as an external trigger signal in
complementary PWM mode and reset-synchronized PWM mode.
When an external trigger occurs, bits 5 to 0 in TOER are cleared to 0, disabling
ITU output.
1 External triggering is disabled
Bits 3 and 2—Reserved: Read-only bits, always read as 1.
6 5
— —
1 1
— —
Reserved bits
External trigger disable
Selects externally triggered disabling of output in
complementary PWM mode and reset-synchronized
PWM mode
Section 10 16-Bit Integrated Timer Unit (ITU)
4 3
XTGD —
1 1
R/W —
Reserved bits
Rev. 7.00 Sep 21, 2005 page 337 of 878
2 1 0
— OLS4 OLS3
1 1 1
— R/W R/W
Output level select 3, 4
These bits select output
levels in complementary
PWM mode and reset-
synchronized PWM mode
(Initial value)
REJ09B0259-0700