Peripheral Clock Select Register (Pclkr); Peripheral Clock Stop Register 1 (Pclkstp1) - Renesas M16C/64C User Manual

M16C/64C Group
8.2.5

Peripheral Clock Select Register (PCLKR)

Peripheral Clock Select Register
b7 b6 b5 b4 b3 b2 b1
0 0 0 0 0
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
PCLK5 (Clock output function extension bit) (b5)
The PCLK5 bit is enabled in single-chip mode. Output from the CLKOUT pin is selectable. When the
PCLK5 bit is 1, set bits CM01 and CM00 to 00b. See Table 8.4 "CLKOUT Pin Functions in Single-Chip
Mode".
8.2.6

Peripheral Clock Stop Register 1 (PCLKSTP1)

Peripheral Clock Stop Register 1
b7 b6 b5 b4 b3 b2 b1 b0
Set the PRC0 bit in the PRCR register to 1 (write enabled) before rewriting this register.
R01UH0092EJ0110 Rev.1.10
Jul 31, 2012
b0 Symbol
PCLKR
Bit Symbol Bit Name
Timers A and B clock select bit
(clock source for timers A and
PCLK0
B, the dead time timer, and
multi-master I
SI/O clock select bit
(clock source for UART0 to
PCLK1
UART2, UART5 to UART7,
SI/O3, and SI/O4)
—
Reserved bits
(b4-b2)
Clock output function
PCLK5 expansion bit
(enabled in single-chip mode)
—
Reserved bits
(b7-b6)
Symbol
PCLKSTP1
Bit Symbol
Peripheral clock stop bit
PCKSTP1A
(other than timer A, timer B)
Timer peripheral clock stop bit
PCKSTP11
(timer A, timer B)
—
No register bit. If necessary, set to 0. The read value is undefined.
(b6-b2)
Timer clock source select bit
PCKSTP17
(timer A, timer B)
Address
0012h
0: f2TIMAB/f2IIC
1: f1TIMAB/f1IIC
2
C-bus interface)
0: f2SIO
1: f1SIO
Set to 0
0: Selected by setting bits CM01 to CM00
in the CM0 register
1: Output f1
Set to 0
Address
0016h
Bit Name
8. Clock Generator
Reset Value
0000 0011b
Function
Reset Value
0XXX XX00b
Function
0: f1 provide enabled
1: f1 provide disabled
0: f1 provide enabled
1: f1 provide disabled
0: f1
1: Main clock
RW
RW
RW
RW
RW
RW
RW
RW
RW
—
RW
Page 93 of 807