Clock Delay Register (Spckd) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.10

Clock Delay Register (SPCKD)

SPCKD sets a period from the beginning of SSL signal assertion to RSPCK oscillation (RSPCK delay) when the
SCKDEN bit in the command register (SPCMD) is 1. If the contents of SPCKD are changed while the MSTR and SPE
bits in the control register (SPCR) are 1 with the function of this module enabled in master mode, the subsequent
operation cannot be guaranteed.
When using this module in slave mode, set B'000 to SCKDL2 to SCKDL0.
Bit Bit Name
7 to 3 ―
2 SCKDL2
1 SCKDL1
0 SCKDL0
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
⎯ ⎯ ⎯
Initial value: 0 0 0
R/W: R R R
Initial Value R/W Function
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R/W RSPCK Delay Setting
0 R/W These bits set an RSPCK delay value when the SCKDEN bit in SPCMD
0 R/W is 1.
The relationship between the setting of SCKDL2 to SCKDL0 and the
RSPCK delay value is shown below.
000: 1 RSPCK
001: 2 RSPCK
010: 3 RSPCK
011: 4 RSPCK
100: 5 RSPCK
101: 6 RSPCK
110: 7 RSPCK
111: 8 RSPCK
16. Renesas Serial Peripheral Interface
4 3 2 1 0
SCK SCK SCK
⎯ ⎯
DL2 DL1 DL0
0 0 0 0 0
R R R/W R/W R/W
16-13