Peripheral Clock Select Register (Pcsr) - Renesas H8S/2100 Series Hardware Manual

9.3.4

Peripheral Clock Select Register (PCSR)

PCSR and the CKS bit of DACR select the operating speed.
Bit Bit Name

7

6
5 PWCKXB
4 PWCKXA

3 to 1
0 PWCKXC
Table 9.3 Clock Select of PWMX
PWCKXC PWCKXB
0 0
0 0
0 1
0 1
1 0
1 0
1 1
1 1
Initial
Value R/W Description
0 R/W Reserved
0 R/W The initial value should not be changed.
0 R/W PWMX clock select
0 R/W These bits select a clock cycle with the CKS bit of
DACR of PWMX being 1.
See table 9.3.
All 0 R/W Reserved
The initial value should not be changed.
0 R/W PWMX clock select
This bit selects a clock cycle with the CKS bit of DACR
of PWMX being 1.
See table 9.3.
PWCKXA
0
1
0
1
0
1
0
1
Section 9 14-Bit PWM Timer (PWMX)
Resolution (T)
Operates on the system clock cycle (t
Operates on the system clock cycle (t
Operates on the system clock cycle (t
Operates on the system clock cycle (t
Operates on the system clock cycle (t
Operates on the system clock cycle (t
Operates on the system clock cycle (t
Setting prohibited
Rev. 1.00 Apr. 28, 2008 Page 225 of 994
) x 2
cyc
) x 64
cyc
) x 128
cyc
) x 256
cyc
) x 1024
cyc
) x 4096
cyc
) x 16384
cyc
REJ09B0452-0100