Peripheral I/O Area Select Control Register (Bpc) - Renesas NU85E Preliminary User's Manual

The programmable peripheral I/O area can be used by specifying the higher 14 bits (bit 27 to bit 14) of the starting
address in the PA00 to PA13 bits of the peripheral I/O area select control register (BPC) and setting (1) the PA15 bit.
The BPC register can be read or written in 16-bit units.
The prioritization of the various CSn areas selected by the VDCSZn signals and the programmable peripheral I/O
area is as follows (n = 7 to 0).
Programmable peripheral I/O area > Various CSn areas selected by VDCSZn signals
Cautions 1. In 64 MB mode, if the programmable peripheral I/O area overlaps the following areas, the
programmable peripheral I/O area becomes invalid.
• • • • Peripheral I/O area
• • • • ROM area
• • • • RAM area
2. In 256 MB mode, if the programmable peripheral I/O area overlaps the following areas, the
programmable peripheral I/O area becomes invalid.
• • • • Peripheral I/O area
• • • • ROM area
• • • • RAM area
• • • • The area that is the same as the RAM area and that is located at address 3FFEFFFH and
below (See Figure 3-8 Data Area (256 MB Mode))
3. If there are no peripheral macros connected to the NPB or user logic, no programmable
peripheral I/O area need be set (Set the BPC register to its after-reset value).
4. When accessing the programmable peripheral I/O area, the VDCSZn signals are all output as
inactive (high level) (n = 7 to 0).
5. Programmable peripheral I/O area address setting is enabled only once. Do not change
address in the middle of a program.
Figure 4-6. Peripheral I/O Area Select Control Register (BPC)
15 14 13
PA PA PA
BPC 0
15 13
Bit position Bit name
15 PA15
13 to 0 PA13 to
PA00
Caution Always set bit 14 to 0. If it is set to 1, operation is not guaranteed.
CHAPTER 4 BCU
12 11 10 9 8 7
PA PA PA PA PA
12 11 10 09 08 07
Sets whether or not the programmable peripheral I/O area can be accessed.
0: It cannot be accessed
1: It can be accessed
Specifies bit 27 to bit 14 of the starting address of the programmable peripheral I/O area.
(The other bits are fixed at zero.)
Preliminary User's Manual A14874EJ3V0UM
6 5 4 3 2 1
PA PA PA PA PA PA
06 05 04 03 02 01
Function
0
PA Address After reset
00 FFFFF064H 0000H
85