Register Configuration; Data Registers (R0, R0H, R0L, R1, R1H, R1L, R2, And R3) - Renesas R8C/Tiny Series Software Manual

Chapter 1 Overview

1.3 Register Configuration

The central processing unit (CPU) contains the 13 registers shown in Figure 1.3.1. Of these registers, R0,
R1, R2, R3, A0, A1, and FB each consist of two sets of registers configuring two register banks.
b31
R2
R3
Note: These registers configure register banks.This register
banks consist of two sets.
Figure 1.3.1 CPU register configuration

1.3.1 Data registers (R0, R0H, R0L, R1, R1H, R1L, R2, and R3)

The data registers (R0, R1, R2, and R3) consist of 16 bits, and are used primarily for transfers and
arithmetic/logic operations.
Registers R0 and R1 can be halved into separate high-order (R0H, R1H) and low-order (R0L, R1L) parts
for use as 8-bit data registers. For some instructions, moreover, you can combine R2 and R0 or R3 and
R1 to configure a 32-bit data register (R2R0 or R3R1).
b15
R0H (High-order of R0)
R1H (High-order of R1)
b19
b15
INTBH
INTBH is the high-order 4 bits of INTB.
INTBL is the low-order 16 bits of INTB.
b19
b15
b15
b15 b8
IPL
b8 b7 b0
R0L (Low-order of R0)
R1L (Low-order of R1)
R2
R3
A0
A1
FB
b0
INTBL
b0
PC
b0
USP
ISP
SB
b0
FLG
b7 b0
U I O B S Z D C
4
1.3 Register Configuration
Data register (Note)
Address register (Note)
Frame base register (Note)
Interrupt table register
Program counter
User stack pointer
Interrupt stack pointer
Static base register
Flag register
Carry flag
Debug flag
Zero flag
Sign flag
Register bank select flag
Overflow flag
Interrupt enable flag
Stack pointer select flag
Reserved area
Processor interrupt priority level
Reserved area