Pwm Data Registers (Pwdr0 To Pwdr15); Pwm Data Polarity Registers A And B (Pwdpra And Pwdprb); Table 10.3 Resolution, Pwm Conversion Period, And Carrier Frequency - Renesas H8S/2158 User Manual

Section 10 8-Bit PWM Timer (PWM)
Table 10.3 Resolution, PWM Conversion Period, and Carrier Frequency when φ φ φ φ = 20 MHz
Internal Clock
Frequency
φ
φ/2
φ/4
φ/8
φ/16
10.3.2

PWM Data Registers (PWDR0 to PWDR15)

PWDR are 8-bit readable/writable registers. The PWM has sixteen PWM data registers. Each
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to a 0 or 1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many extra pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for 0/1 ratios
within the conversion period. For 256/256 (100%) output, port output should be used.
10.3.3

PWM Data Polarity Registers A and B (PWDPRA and PWDPRB)

Each PWDPR selects the PWM output phase.
PWDPRA
Bit Bit Name Initial Value
7 OS7 0
6 OS6 0
5 OS5 0
4 OS4 0
3 OS3 0
2 OS2 0
1 OS1 0
0 OS0 0
Rev. 3.00 Jan 25, 2006 page 266 of 872
REJ09B0286-0300
Resolution
50 ns
100 ns
200 ns
400 ns
800 ns
R/W Description
R/W Output Select 7 to 0
R/W
These bits select the PWM output phase. Bits OS7 to
R/W
OS0 correspond to outputs PW7 to PW0.
R/W
0: PWM direct output (PWDR value corresponds to high
R/W
R/W
R/W
1: PWM inverted output (PWDR value corresponds to
R/W
PWM Conversion
Period
12.8 µs
25.6 µs
51.2 µs
102.4 µs
204.8 µs
width of output)
low width of output)
Carrier Frequency
1250 kHz
625 kHz
312.5 kHz
156.3 kHz
78.1 kHz