Pwm Data Registers 7 To 0 (Pwdr7 To Pwdr0); Table 8.2 Internal Clock Selection; Table 8.3 Resolution, Pwm Conversion Period, And Carrier Frequency When Φ = 20 Mhz - Renesas H8S/2437 Hardware Manual

Table 8.2 Internal Clock Selection
PWSL
PWCKE PWCKS
0 —
1 0
1
Resolution, PWM Conversion Period, and Carrier Frequency when φ φ φ φ = 20 MHz
Table 8.3
Internal Clock
Frequency
φ
φ/2
φ/4
φ/8
φ/16
8.3.2

PWM Data Registers 7 to 0 (PWDR7 to PWDR0)

PWDR are 8-bit readable/writable registers. The PWM has eight PWM data registers. Each
PWDR specifies the duty cycle of the basic pulse to be output, and the number of additional
pulses. The value set in PWDR corresponds to the 0/1 ratio in the conversion period. The upper
four bits specify the duty cycle of the basic pulse as 0/16 to 15/16 with a resolution of 1/16. The
lower four bits specify how many additional pulses are to be added within the conversion period
comprising 16 basic pulses. Thus, a specification of 0/256 to 255/256 is possible for the 0/1 ratio
within the conversion period. For 256/256 (100%) output, port output should be used.
Rev. 1.00, 09/03, page 220 of 704
PCSR
PWCKB PWCKA
— —
— —
0 0
1
1 0
1
Resolution
50 ns
100 ns
200 ns
400 ns
800 ns
Description
Clock input is disabled
φ (system clock) is selected
φ/2 is selected
φ/4 is selected
φ/8 is selected
φ/16 is selected
PWM Conversion
Period
12.8 µs
25.6 µs
51.2 µs
102.4 µs
204.8 µs
(Initial value)
Carrier Frequency
1250 kHz
625 kHz
312.5 kHz
156.3 kHz
78.13 kHz