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Bit 0—Clock Select 0 (PWCR0): Bit 0 selects the clock supplied to the 14-bit PWM. This bit is a
write-only bit; it is always read as 1.
Bit 0: PWCR0
Description
The input clock is φ/2 (t
0
minimum modulation width of 1/φ.
The input clock is φ/4 (t
1
minimum modulation width of 2/φ.
φ
Note: t
: Period of PWM input clock
11.2.2
PWM Data Registers U and L (PWDRU, PWDRL)
Bit
PWDRU
Initial value
Read/Write
Bit
PWDRL
PWDRL7 PWDRL6 PWDRL5 PWDRL4 PWDRL3 PWDRL2 PWDRL1 PWDRL0
Initial value
Read/Write
PWDRU and PWDRL form a 14-bit write-only register, with the upper 6 bits assigned to PWDRU
and the lower 8 bits to PWDRL. The value written to PWDRU and PWDRL gives the total high-
level width of one PWM waveform cycle.
When 14-bit data is written to PWDRU and PWDRL, the register contents are latched in the PWM
waveform generator, updating the PWM waveform generation data. The 14-bit data should always
be written in the following sequence, first to PWDRL and then to PWDRU.
1. Write the lower 8 bits to PWDRL.
2. Write the upper 6 bits to PWDRU.
PWDRU and PWDRL are write-only registers. If they are read, all bits are read as 1.
Upon reset, PWDRU and PWDRL are initialized to H'C000.
7
6
5
⎯
⎯
PWDRU5 PWDRU4 PWDRU3 PWDRU2 PWDRU1 PWDRU0
1
1
0
⎯
⎯
W
7
6
5
0
0
0
W
W
W
11. 14-Bit PWM (H8/3857 Group Only)
∗ = 2/φ). The conversion period is 16,384/φ, with a
φ
∗ = 4/φ). The conversion period is 32,768/φ, with a
φ
4
3
0
0
W
W
4
3
0
0
W
W
Rev.3.00 Jul. 19, 2007 page 313 of 532
(initial value)
2
1
0
0
W
W
W
2
1
0
0
W
W
W
REJ09B0397-0300
0
0
0
0
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