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15.2
Register Descriptions
15.2.1
A/D Data Registers A to D (ADDRA to ADDRD)
Bit
15
ADDRn
AD9
Initial value
0
Read/Write
R
(n = A to D)
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the upper
byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of an A/D
data register are reserved bits that are always read as 0. Table 15.3 indicates the pairings of analog
input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 15.3, CPU
Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 15.3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0
Group 1
AN
AN
0
4
AN
AN
1
5
AN
AN
2
6
AN
AN
3
7
14
13
12
11
10
AD8
AD7
AD6
AD5
AD4
0
0
0
0
0
R
R
R
R
R
A/D conversion data
10-bit data giving an
A/D conversion result
A/D Data Register
ADDRA
ADDRB
ADDRC
ADDRD
9
8
7
6
AD3
AD2
AD1
AD0
0
0
0
0
R
R
R
R
R
Rev. 4.00 Jan 26, 2006 page 573 of 938
Section 15 A/D Converter
5
4
3
2
1
0
0
0
0
0
R
R
R
R
Reserved bits
REJ09B0276-0400
0
0
R
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