Pwm D/A Control Register (Dacr) - Renesas H8S/2633 Series Hardware Manual

Bit 1—Carrier Frequency Select (CFS)
Bit 1
CFS Description
Base cycle = resolution (T) × 64
0
DADR range = H'0401 to H'FFFD
Base cycle = resolution (T) × 256
1
DADR range = H'0103 to H'FFFF
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
DADRB Bit 0—Register Select (REGS): DADRA and DACR, and DADRB and DACNT, are
located at the same addresses. The REGS bit specifies which registers can be accessed. The REGS
bit can be accessed regardless of whether DADRB or DACNT is selected.
Bit 0
REGS Description
0 DADRA and DADRB can be accessed
1 DACR and DACNT can be accessed
14.2.3

PWM D/A Control Register (DACR)

Bit : 7
TEST
Initial value : 0
R/W : R/W
DACR is an 8-bit readable/writable register that selects test mode, enables the PWM outputs, and
selects the output phase and operating speed.
DACR is initialized to H'30 by a reset, and in the standby modes, watch mode, subactive mode,
subsleep mode, and module stop mode.
660
6 5
PWME —
0 1
R/W —
4 3 2
— OEB OEA
1 0 0
— R/W R/W
(Initial value)
(Initial value)
1 0
OS CKS
0 0
R/W R/W