Pwm Register Select (Pwsl) - Renesas H8S/2437 Hardware Manual

8.3.1

PWM Register Select (PWSL)

PWSL selects the input clock and the PWM data register.
Bit Bit Name Initial Value
7 PWCKE 0
6 PWCKS 0
5 — 1
4 — 0
3 — 0
2 RS2 0
1 RS1 0
0 RS0 0
R/W Description
R/W PWM Clock Enable
R/W PWM Clock Select
These bits, together with bits PWCKB and PWCKA in
PCSR, select the internal clock input to TCNT of the
PWM. For details, see table 8.2.
The resolution, PWM conversion period, and carrier
frequency depend on the selected internal clock, and
can be obtained from the following equations.
Resolution (minimum pulse width) = 1/internal clock
frequency
PWM conversion period = resolution × 256
Carrier frequency = 16/PWM conversion period
With the 20-MHz system clock (φ), the resolution, PWM
conversion period, and carrier frequency are as shown
in table 8.3.
R Reserved
This bit is always read as 1 and cannot be modified.
R Reserved
This bit is always read as 0 and cannot be modified.
R/W Reserved
The initial value should not be changed.
R/W Register Select
R/W
These bits select the PWM data register.
R/W
000: PWDR0 selected
001: PWDR1 selected
010: PWDR2 selected
011: PWDR3 selected
100: PWDR4 selected
101: PWDR5 selected
110: PWDR6 selected
111: PWDR7 selected
Rev. 1.00, 09/03, page 219 of 704