Slave Select Polarity Register (Sslp); Pin Control Register (Sppcr) - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
16.3.2

Slave Select Polarity Register (SSLP)

SSLP sets the polarity of the SSL signal. If the contents of SSL0P are changed while the function of this module is
enabled by setting the SPE bit in the control register (SPCR) to 1, subsequent operations cannot be guaranteed.
Bit Bit Name
7 to 1 ―
0 SSL0P
16.3.3

Pin Control Register (SPPCR)

SPPCR sets the modes of the pins. If the contents of this register are changed while the function of this module is enabled
by setting the SPE bit in the control register (SPCR) to 1, subsequent operations cannot be guaranteed.
Bit Bit Name
7, 6 ―
5 MOIFE
4 MOIFV
3 to 1 ―
0 SPLP
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
Bit: 7 6 5
⎯ ⎯ ⎯
Initial value: 0 0 0
R/W: R R R
Initial Value R/W Function
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R/W SSL Signal Polarity Setting
Sets the polarity of the SSL signal. The value of SSL0P indicates the
active polarity of the SSL signal.
0: SSL signal 0-active
1: SSL signal 1-active
Bit: 7 6 5
⎯ ⎯
MOIFE MOIFV
Initial value: 0 0 0
R/W:
R R R/W
Initial Value R/W Function
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R/W MOSI Idle Value Fixing Enable
Fixes the MOSI output value when this module in master mode is in an
SSL negation period (including the SSL retention period during a burst
transfer). When MOIFE is 0, this module outputs the last output value
from the previous serial transfer during the SSL negation period to the
MOSI pin. (The value is undefined when CPHA is 0). When MOIFE is 1,
this module outputs the fixed value set in the MOIFV bit to the MOSI pin.
0: MOSI output value equals the last output value from previous transfer.
1: MOSI output value equals the value set in the MOIFV bit.
0 R/W MOSI Idle Fixed Value
If the MOIFE bit is 1 in master mode, this module, according to MOIFV bit
settings, determines the MOSI signal value during the SSL negation
period (including the SSL retention period during a burst transfer).
0: MOSI Idle fixed value equals 0.
1: MOSI Idle fixed value equals 1.
All 0 R Reserved
The write value should always be 0. Otherwise, operation cannot be
guaranteed.
0 R/W Loopback
When the SPLP bit is set to 1, this module shuts off the path between the
MISO pin and the shift register, and between the MOSI pin and the shift
register, and connects (reverses) the input path and the output path for
the shift register.
0: Normal mode
1: Loopback mode
16. Renesas Serial Peripheral Interface
4 3 2 1
⎯ ⎯ ⎯ ⎯
SSL0P
0 0 0 0
R R R R
4 3 2 1
⎯ ⎯ ⎯
SPLP
0 0 0 0
R/W R R R
(The value is undefined when CPHA is 0).
0
0
R/W
0
0
R/W
16-7